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Yunpeng Yin

from Clifton Park, NY
Age ~47
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Also known as:
Yun Peng Yin, Yun-Peng Yin, Peng Yin Yun, Ying Yupeng, Yin G
Phone and address:
8 Sherman Oaks, Clifton Park Center, NY 12065
Related to:
Lu Yun, 42
Connected to:
Alice C Yin, 67Angela H Yin, 42Anita Yin, 51Boqun Yin, 40Calvin Yin, 31Cathy L Yin, 71Chu C Yin, 71Chunfeng Yin, 61Chunkai Yin, 50Connie K Yin, 52

Yunpeng Yin Phones & Addresses

  • 8 Sherman Oaks, Clifton Park, NY 12065
  • 2 Oakline Ct, Niskayuna, NY 12309 (518) 357-3370
  • Schenectady, NY
  • 3 Winding Brook Dr, Guilderland, NY 12084 (518) 608-4156
  • Cambridge, MA

Work

Company: Pdf solutions Apr 2013 Position: Senior consulting engineer

Education

Degree: PhD School / High School: Massachusetts Institute of Technology 2002 to 2007 Specialities: Chemical Engineering

Skills

Thin Films • Materials Science

Industries

Semiconductors

Resumes

Resumes

Yunpeng Yin Photo 1

Senior Consulting Engineer

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Position:
Senior Consulting Engineer at PDF Solutions
Location:
Albany, New York Area
Industry:
Semiconductors
Work:
PDF Solutions since Apr 2013
Senior Consulting Engineer
IBM Jan 2012 - Apr 2013
FEOL fin, gate patterning etch engineer, team lead
IBM Jan 2012 - Apr 2013
Pathfinding etch process engineer, team lead
IBM Oct 2009 - Dec 2011
Advanced patterning etch process engineer, team lead
IBM Jul 2007 - Sep 2009
BEOL Etch process Engineer
Education:
Massachusetts Institute of Technology 2002 - 2007
PhD, Chemical Engineering Tsinghua University 1999 - 2002
MS, chemical engineering Tsinghua University 1995 - 1999
BE, Chemical Engineering
Skills:
Thin Films
Materials Science

Publications

Us Patents

Self Aligning Via Patterning

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US Patent:
8298943, Oct 30, 2012
Filed:
May 27, 2011
Appl. No.:
13/118034
Inventors:
John Christopher Arnold - North Chatham NY, US
Sean D. Burns - Hopewell Junction NY, US
Sivananda K. Kanakasabapathy - Niskayuna NY, US
Yunpeng Yin - Niskayuna NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/311
H01L 21/44
US Classification:
438667, 438694, 438704, 438734, 438669, 438672
Abstract:
A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. The first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch.

Sidewall Image Transfer Process Employing A Cap Material Layer For A Metal Nitride Layer

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US Patent:
8298954, Oct 30, 2012
Filed:
May 6, 2011
Appl. No.:
13/102224
Inventors:
John C. Arnold - Valatie NY, US
Sean D. Burns - Hopewell Junction NY, US
Matthew E. Colburn - Schenectady NY, US
David V. Horak - Essex Junction VT, US
Yunpeng Yin - Guilderland NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/311
H01L 21/302
US Classification:
438703, 438737, 438738, 257E21235, 257E21305
Abstract:
A cap material layer is deposited on a metal nitride layer. An antireflective coating (ARC) layer, an organic planarizing layer (OPL), and patterned line structures are formed upon the cap material layer. The pattern in the patterned line structures is transferred into the ARC layer and the OPL. Exposed portions of the cap material layer are etched simultaneously with the etch removal of the patterned line structures and the ARC layer. The OPL is employed to etch the metal nitride layer. The patterned cap material layer located over the metal nitride layer protects the top surface of the metal nitride layer, and enables high fidelity reproduction of the pattern in the metal nitride layer without pattern distortion. The metal nitride layer is subsequently employed as an etch mask for pattern transfer into an underlying layer.

Tone Inversion With Partial Underlayer Etch For Semiconductor Device Formation

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US Patent:
8470711, Jun 25, 2013
Filed:
Nov 23, 2010
Appl. No.:
12/952248
Inventors:
John C. Arnold - North Chatham NY, US
Sean D. Burns - Hopewell Junction NY, US
Matthew E. Colburn - Schenectady NY, US
Steven J. Holmes - Guilderland NY, US
Yunpeng Yin - Niskayuna NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/44
US Classification:
438674, 438703, 257499
Abstract:
A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate. A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer.

Self Aligning Via Patterning

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US Patent:
8518824, Aug 27, 2013
Filed:
Jul 26, 2012
Appl. No.:
13/558441
Inventors:
John Christopher Arnold - North Chatham NY, US
Sean D. Burns - Hopewell Junction NY, US
Sivananda K. Kanakasabapathy - Niskayuna NY, US
Yunpeng Yin - Niskayuna NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/311
H01L 21/44
H01L 21/00
US Classification:
438667, 438694, 438704, 438734, 438669, 438672, 257E21002
Abstract:
A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Then, form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. Then the first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch.

Film Stack Including Metal Hardmask Layer For Sidewall Image Transfer Fin Field Effect Transistor Formation

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US Patent:
8580692, Nov 12, 2013
Filed:
Jun 29, 2011
Appl. No.:
13/171865
Inventors:
John C. Arnold - North Chatham NY, US
Sivananda K. Kanakasabapathy - Niskayuna NY, US
Stefan Schmitz - Malta NY, US
Yunpeng Yin - Guilderland NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/311
US Classification:
438706, 257618, 257E21314
Abstract:
A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask and a large feature (FX) mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; and etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.

Film Stack Including Metal Hardmask Layer For Sidewall Image Transfer Fin Field Effect Transistor Formation

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US Patent:
8586482, Nov 19, 2013
Filed:
Jun 29, 2011
Appl. No.:
13/171868
Inventors:
John C. Arnold - North Chatham NY, US
Sivananda K. Kanakasabapathy - Niskayuna NY, US
Stefan Schmitz - Malta NY, US
Yunpeng Yin - Guilderland NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/311
US Classification:
438706, 257618, 257E21314
Abstract:
A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; forming a large feature (FX) mask on the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.

Image Transfer Process Employing A Hard Mask Layer

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US Patent:
8637406, Jan 28, 2014
Filed:
Jul 19, 2012
Appl. No.:
13/552992
Inventors:
Ryan O. Jung - Rensselaer NY, US
Sivananda K. Kanakasabapathy - Niskayuna NY, US
Yunpeng Yin - Niskayuna NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/311
US Classification:
438703
Abstract:
At least one mask layer formed over a substrate includes at least one of a dielectric material and a metallic material. By forming a first pattern in one of the at least one mask layer, a patterned mask layer including said first pattern is formed. An overlying structure including a second pattern that includes at least one blocking area is formed over said patterned mask layer. Portions of said patterned mask layer that do not underlie said blocking area are removed. The remaining portions of the patterned mask layer include a composite pattern that is an intersection of the first pattern and the second pattern. The patterned mask layer includes a dielectric material or a metallic material, and thus, enables high fidelity pattern transfer into an underlying material layer.

Sidewall Image Transfer Process

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US Patent:
20120244711, Sep 27, 2012
Filed:
Mar 23, 2011
Appl. No.:
13/069536
Inventors:
Yunpeng Yin - Albany NY, US
John C. Arnold - Albany NY, US
Matthew E. Colburn - Yorktown Heights NY, US
Sean D. Burns - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/31
US Classification:
438703, 257E2124
Abstract:
An improved method of performing sidewall spacer imager transfer is presented. The method includes forming a set of sidewall spacers next to a plurality of mandrels, the set of sidewall spacers being directly on top of a hard-mask layer; transferring image of at least a portion of the set of sidewall spacers to the hard-mask layer to form a device pattern; and transferring the device pattern from the hard-mask layer to a substrate underneath the hard-mask layer.
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Yunpeng Yin from Clifton Park, NY, age ~47 Get Report