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Xiaopeng Qu Phones & Addresses

  • Redmond, WA
  • Bellevue, WA
  • 4193 E Carnation Ct, Boise, ID 83716
  • Cayce, SC
  • Durham, NC

Work

Company: Duke university Feb 2012 Position: Postdoctoral associate and research scientist

Education

School / High School: Hong Kong University of Science and Technology- Hong Kong, Hong Kong Island Sep 2005 Specialities: Ph.D. in Mechanical Engineering

Skills

thermal management (electronic cooling);... • fabrication • simulation); microfluidics (lab-on-a-chip)

Industries

Information Technology and Services

Resumes

Resumes

Xiaopeng Qu Photo 1

Software Development Engineer In Test At Microsoft

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Position:
Software Development Engineer in Test at Microsoft
Location:
Greater Seattle Area
Industry:
Information Technology and Services
Work:
Microsoft since Jul 2010
Software Development Engineer in Test

Microsoft Mar 2009 - Jul 2009
Software Development Engineer in Test

Microsoft Canada Development Center Oct 2007 - Mar 2009
Software Development Engineer in Test
Education:
Acadia University 2001 - 2004
BCS, Computer Science
Xiaopeng Qu Photo 2

Xiaopeng Qu Durham, NC

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Work:
Duke University

Feb 2012 to 2000
Postdoctoral Associate and Research Scientist

Max-Planck-Institute

Oct 2010 to Dec 2011
Postdoctoral Research Fellow

Hong Kong University of Science and Technology
Hong Kong, Hong Kong Island
Sep 2005 to Aug 2010
Ph.D. Research Assistant

University of Chinese Academy of Sciences

Sep 2002 to Jul 2005
M.S. Research Assistant

Education:
Hong Kong University of Science and Technology
Hong Kong, Hong Kong Island
Sep 2005 to Aug 2010
Ph.D. in Mechanical Engineering

University of Chinese Academy of Sciences
Sep 2002 to Jul 2005
M.S. in Mechanical Engineering

Shandong University
Jinan, CN
Sep 1998 to Jul 2002
B.S. in Thermal Engineering

Skills:
thermal management (electronic cooling); MEMS (design, fabrication, simulation); microfluidics (lab-on-a-chip)

Publications

Us Patents

Semiconductor Devices With Flexible Connector Array

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US Patent:
20220285281, Sep 8, 2022
Filed:
May 23, 2022
Appl. No.:
17/750665
Inventors:
- Boise ID, US
Xiaopeng Qu - Boise ID, US
International Classification:
H01L 23/538
H05K 1/18
H01L 23/498
H01L 23/00
Abstract:
A semiconductor device includes an array of flexible connectors configured to mitigate thermomechanical stresses. In one embodiment, a semiconductor assembly includes a substrate coupled to an array of flexible connectors. Each flexible connector can be transformed between a resting configuration and a loaded configuration. Each flexible connector includes a conductive wire electrically coupled to the substrate and a support material at least partially surrounding the conductive wire. The conductive wire has a first shape when the flexible connector is in the resting configuration and a second, different shape when the flexible connector is in the loaded configuration. The first shape includes at least two apices spaced apart from each other in a vertical dimension by a first distance, and the second shape includes the two apices spaced apart from each other in the vertical dimension by a second distance different than the first distance.

Substrates For Semiconductor Device Assemblies And Systems With Improved Thermal Performance And Methods For Making The Same

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US Patent:
20210407882, Dec 30, 2021
Filed:
Oct 1, 2020
Appl. No.:
17/061435
Inventors:
- Boise ID, US
Xiaopeng Qu - Boise ID, US
Chan H. Yoo - Boise ID, US
International Classification:
H01L 23/373
H01L 23/00
H01L 23/498
H01L 23/367
Abstract:
Semiconductor device assemblies are provided with a package substrate including one or more layers of thermally conductive material configured to conduct heat generated by one or more of semiconductor dies of the assemblies laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), via adhering a film comprising the layer of thermally conductive material to an outer surface of the package substrate, or via embedding a film comprising the layer of thermally conductive material to within the package substrate.

Semiconductor Device Assemblies And Systems With Improved Thermal Performance And Methods For Making The Same

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US Patent:
20210407964, Dec 30, 2021
Filed:
Jul 27, 2020
Appl. No.:
16/939449
Inventors:
- Boise ID, US
Xiaopeng Qu - Boise ID, US
International Classification:
H01L 25/065
H01L 23/31
H01L 23/373
H01L 25/00
H01L 21/56
Abstract:
Semiconductor device assemblies are provided with one or more layers of thermally conductive material disposed between adjacent semiconductor dies in a vertical stack. The thermally conductive material can be configured to conduct heat generated by one or more of the semiconductor dies in laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), or via adhering a film comprising the layer of thermally conductive material to one or more of the semiconductor dies.

Lidded Microelectronic Device Packages And Related Systems, Apparatus, And Methods Of Manufacture

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US Patent:
20210391235, Dec 16, 2021
Filed:
Jun 16, 2020
Appl. No.:
16/902390
Inventors:
- Boise ID, US
Xiaopeng Qu - Redmond WA, US
International Classification:
H01L 23/367
H01L 23/373
H01L 23/31
Abstract:
A microelectronic device package may include one or more semiconductor dice coupled to a substrate. The microelectronic device package may further include a lid coupled to the substrate, the lid defining a volume over and around the one or more semiconductor die. The microelectronic device package may further include a thermally conductive dielectric filler material substantially filling the volume defined around the semiconductor die.

Semiconductor Devices With Flexible Connector Array

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US Patent:
20210272908, Sep 2, 2021
Filed:
Feb 27, 2020
Appl. No.:
16/803954
Inventors:
- Boise ID, US
Xiaopeng Qu - Boise ID, US
International Classification:
H01L 23/538
H01L 23/00
H01L 23/498
H05K 1/18
Abstract:
Semiconductor devices having an array of flexible connectors configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor assembly includes a substrate coupled to an array of flexible connectors. Each flexible connector can be transformed between a resting configuration and a loaded configuration. Each flexible connector can include a conductive wire electrically coupled to the substrate and a support material at least partially surrounding the conductive wire. The conductive wire can have a first shape when the flexible connector is in the resting configuration and a second, different shape when the flexible connector is in the loaded configuration.

Heat Spreaders For Multiple Semiconductor Device Modules

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US Patent:
20200286805, Sep 10, 2020
Filed:
May 26, 2020
Appl. No.:
16/884030
Inventors:
- Boise ID, US
Xiaopeng Qu - Boise ID, US
International Classification:
H01L 23/367
H05K 7/20
G06F 1/20
Abstract:
A heat spreader for use in a memory system is provided, including a thermally conductive body having a first planar side surface and a second planar side surface opposite the first planar side surface, the first planar side surface configured to attach to a first plurality of co-planar semiconductor devices of a first memory module of the memory system, the second planar side surface configured to attach to a second plurality of co-planar semiconductor devices of a second memory module of the memory system, wherein the first planar side surface and the second planar side surface are separated by a body width w substantially equal to a distance between the first plurality of co-planar semiconductor devices and the second plurality of co-planar semiconductor devices.

Heat Spreaders For Multiple Semiconductor Device Modules

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US Patent:
20200075451, Mar 5, 2020
Filed:
Aug 31, 2018
Appl. No.:
16/118889
Inventors:
- Boise ID, US
Xiaopeng Qu - Boise ID, US
International Classification:
H01L 23/367
H05K 7/20
G06F 1/20
Abstract:
A heat spreader for use in a memory system is provided, including a thermally conductive body having a first planar side surface and a second planar side surface opposite the first planar side surface, the first planar side surface configured to attach to a first plurality of co-planar semiconductor devices of a first memory module of the memory system, the second planar side surface configured to attach to a second plurality of co-planar semiconductor devices of a second memory module of the memory system, wherein the first planar side surface and the second planar side surface are separated by a body width w substantially equal to a distance between the first plurality of co-planar semiconductor devices and the second plurality of co-planar semiconductor devices.

Assemblies Including Heat Dispersing Elements And Related Systems And Methods

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US Patent:
20190132995, May 2, 2019
Filed:
Oct 27, 2017
Appl. No.:
15/795690
Inventors:
- Boise ID, US
Xiaopeng Qu - Boise ID, US
International Classification:
H05K 7/20
H05K 7/14
H05K 1/18
F28F 3/02
Abstract:
Assemblies include at least one substrate, at least one electronic device coupled to the substrate, and heat dissipation elements. The heat dissipation elements comprises at least one heat spreader in communication with the at least one electronic device and at least one heat sink in communication with the at least one heat spreader. Methods of dissipating heat energy includes transferring heat energy from memory devices to heat spreaders positioned adjacent to the memory devices and transferring the heat energy from the heat spreaders to a heat sink.
Xiaopeng Qu from Redmond, WA, age ~44 Get Report