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Vikram L Kowshik

from Cupertino, CA
Age ~70
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Also known as:
Vikram Renu Kowshik, Vikram K
Phone and address:
10467 Anson Ave, Cupertino, CA 95014
(408) 252-6226
Related to:
Karen J Shender, 79Dilip Basu, 45Jayant Kowshik, 32Dilip K Basu, 86Vinay Kowshik, 30Jayant Kowshik, 68Renu Kowshik, 62Basen Dayani, 72Dayani K Basu, 72
Connected to:
Hemant J Kowshik, 41Sangeetha L Kowsik, 45June M Kowski, 56Sharon L Kowski, 69Brandon C Kowsky, 52Peter Kowsun, 98Stacy J Kowsz, 37Keith N Kowta, 56Michael B Kowtko, 67Walter E Kowtoniuk, 42

Vikram Kowshik Phones & Addresses

  • 10467 Anson Ave, Cupertino, CA 95014 (408) 252-6226
  • 2094 Limewood Dr, San Jose, CA 95132
  • Fremont, CA
  • Clemson, SC
  • Capitola, CA
  • Santa Clara, CA
  • 10467 Anson Ave, Cupertino, CA 95014

Resumes

Resumes

Vikram Kowshik Photo 1

Design Engineering Fellow

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Location:
10467 Anson Ave, Cupertino, CA 95014
Industry:
Semiconductors
Work:
Atmel Corporation
Design Engineering product line manager
Atmel Corporation since 1998
Design Manager Flash Product Line
Programmable Microelectronics Corp. 1995 - 1998
Design Engineering Director
Education:
Indian Institute of Technology
Bachelors, Bachelor of Science In Electrical Engineering, Bachelor of Technology, Electronics Engineering, Electronics Clemson University
Masters, Master of Science In Electrical Engineering, Communications, Engineering, Electronics
Skills:
Semiconductors
Cmos
Mixed Signal
Ic
Asic
Start Ups
Interests:
Exercise
Home Improvement
Reading
Gourmet Cooking
Sports
Home Decoration
Photograph
Cooking
Cruises
Outdoors
Electronics
Crafts
Music
Camping
Family Values
Movies
Christianity
Automobiles
Travel
Boating
Investing
Traveling
Tennis
Languages:
English
Vikram Kowshik Photo 2

Design Manager

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Atmel Corporation
Design Manager
Vikram Kowshik Photo 3

Vikram Kowshik

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Publications

Us Patents

Functional Register Decoding System For Multiple Plane Operation

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US Patent:
7099226, Aug 29, 2006
Filed:
Oct 14, 2003
Appl. No.:
10/686401
Inventors:
Yolanda Yuan - Saratoga CA, US
Jason Guo - San Jose CA, US
Sai K. Tsang - Union City CA, US
Vikram Kowshik - Cupertino CA, US
Steven J. Schumann - Sunnyvale CA, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G11C 8/00
US Classification:
36523003, 36523006, 36518904
Abstract:
A decoding system for multi-plane memories routes address information corresponding to distinct memory access operations to the designated planes. The system includes an array of functional registers dedicated to random access read, burst read, program, erase, and erase-suspend program operations. Plane selector blocks for each plane receive the address outputs from all of the registers and plane function select logic controls the routing in accord with memory access commands for specified planes. Simultaneous operations of different type in different planes and nested operations in the same plane are possible.

Method And Apparatus Of A Smart Decoding Scheme For Fast Synchronous Read In A Memory System

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US Patent:
7143257, Nov 28, 2006
Filed:
Oct 14, 2003
Appl. No.:
10/686243
Inventors:
Vikram Kowshik - Cupertino CA, US
Fai Ching - Fremont CA, US
Steven J. Schumann - Sunnyvale CA, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G06F 12/00
G06F 13/00
US Classification:
711167, 711100, 711154
Abstract:
An apparatus and method identify a plurality of words to be read, read these selected words during a clock latency period, and then shift these words out synchronously at an end of the latency period. In another aspect of the present invention, the above method of reading a plurality of words during a clock latency period and shifting them out synchronously after the latency period is facilitated by a two tier column decoder. The two-tier column decoder has two decoders. A first-tier decoder decodes a first group of words to be read during the latency period, and a second-tier decoder decodes subsequent words to be shifted out synchronously during a burst period.

Programmable Memory Data Protection Scheme

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US Patent:
49758780, Dec 4, 1990
Filed:
Sep 18, 1989
Appl. No.:
7/409958
Inventors:
Sudhakar Boddu - Sunnyvale CA
Vikram Kowshik - San Jose CA
Elroy M. Lucero - San Jose CA
Assignee:
National Semiconductor - Santa Clara CA
International Classification:
G11C 1606
US Classification:
36518907
Abstract:
An integrated, non-volatile memory protect register is provided for the memory array of a monolithic integrated circuit device. The memory array includes a plurality of programmable data storage registers, each having an associated address. The storage register addresses define the storage registers sequentially from an initial register in the array to a final register in the array. The memory protect register stores the address of a preselected storage register in the array. All registers in the array having addresses equal to or greater than the address of the preselected register are protected from any write operation. This address can be "locked" into the memory protect register to provide permanent data security to all protected registers.

Two-Transistor Electrically-Alterable Switch Employing Hot Electron Injection And Fowler Nordheim Tunneling

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US Patent:
56252110, Apr 29, 1997
Filed:
Jan 12, 1995
Appl. No.:
8/371685
Inventors:
Vikram Kowshik - Fremont CA
Assignee:
Actel Corporation - Sunnyvale CA
International Classification:
H01L 29788
H01L 27108
US Classification:
257317
Abstract:
An electrically-alterable switch includes a floating gate EEPROM transistor having a source, a drain, a control gate, and a floating gate. A select transistor includes a source capacitively coupled to the floating gate of the EEPROM transistor via a tunneling oxide, a drain, and a gate. A pass transistor, having a source, a drain, and a gate comprising a portion of the floating gate may be included in the structure.

Pmos Non-Volatile Latch For Storage Of Redundancy Addresses

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US Patent:
57814716, Jul 14, 1998
Filed:
Aug 15, 1997
Appl. No.:
8/911816
Inventors:
Vikram Kowshik - San Jose CA
Andy Teng-Feng Yu - Palo Alto CA
Assignee:
Programmable Microelectronics Corporation - San Jose CA
International Classification:
G11C 1300
US Classification:
36518507
Abstract:
A non-volatile memory latch device includes two PMOS memory cells and a cross-coupled static latch having two PMOS transistors and two NMOS transistors. The floating gates of each PMOS memory cell/transistor pair are coupled together. The control gates of all four PMOS devices are commonly connected to an input. The latch is programmed by applying -3 to -8 volts to the drain of one of the PMOS memory cells, floating the drain of the other PMOS memory cell, and applying 7 to 11 volts to the control gates of all four PMOS devices. The latch is erased by applying 3 to 8 volts to both drains of the PMOS memory cells and -7 to -11 volts to the control gates of all four PMOS devices. Lower programming and erasing voltages are possible with the PMOS latch, as compared with conventional NMOS latches.

Switching Circuit For Controlled Transition Between High Program And Erase Voltages And A Power Supply Voltage For Memory Cells

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US Patent:
57744068, Jun 30, 1998
Filed:
Oct 3, 1996
Appl. No.:
8/722429
Inventors:
Vikram Kowshik - Fremont CA
Assignee:
Programmable Microelectronic Corporation - San Jose CA
International Classification:
G11C 702
US Classification:
365226
Abstract:
A switching circuit is disclosed herein which prevents an unwanted forward biasing of P/N junctions therein while allowing voltages exceeding the supply voltage to be provided in a precise manner to such floating gate memory cells. In accordance with the present invention, a switching circuit includes a first stage which effectively isolates programming voltages from supply voltages during programming and erasing operations, thereby allowing program and erase voltages exceeding supply voltage to be provided to an associated memory array. The switching circuit includes a second stage which prevents the unwanted forward-biasing of P/N junctions within the switch and its associated memory array by controlling the discharge rate of internal node when transitioning from either a programming or erasing operation to a read operation.

Page Buffer Having Negative Voltage Level Shifter

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US Patent:
59739673, Oct 26, 1999
Filed:
Dec 5, 1997
Appl. No.:
8/985561
Inventors:
Chinh D. Nguyen - San Jose CA
Andy Teng-Feng Yu - Palo Alto CA
Vikram Kowshik - San Jose CA
Vishal Sarin - Santa Clara CA
Assignee:
Programmable Microelectronics Corporation - San Jose CA
International Classification:
G11C 1604
G11C 1100
US Classification:
36518905
Abstract:
A page buffer facilitates programming of a memory cell within an associated memory array by selectively connecting a bit line associated with the memory cell to a negative voltage supply in response to the logic state of a data signal. The page buffer includes an SRAM latch having first and second nodes, a cross-coupled latch having first and second nodes, and a pass transistor. The first node of the SRAM latch is coupled to receive the data signal and to a first control terminal of the cross-coupled latch. The second node of the SRAM latch is coupled to a second control terminal of the cross-coupled latch. The second node of the cross-coupled latch is coupled to a gate of the pass transistor which, in turn, is connected between the bit line and the negative voltage supply. When the data signal is in a first logic state, the cross-coupled latch turns on the pass transistor and, in connecting the bit line to the negative voltage supply, facilitates programming of the cell. When the data signal is in a second logic state, the cross-coupled latch turns off the pass transistor and allows the bit line to float which, in turn, precludes programming of the cell.

Programming Pulse Ramp Control Circuit

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US Patent:
56871163, Nov 11, 1997
Filed:
Oct 9, 1996
Appl. No.:
8/727875
Inventors:
Vikram Kowshik - San Jose CA
Andy Teng-Feng Yu - Palo Alto CA
Assignee:
Programmable Microelectronics Corp. - San Jose CA
International Classification:
G11C 1134
US Classification:
36518503
Abstract:
A pulse ramp control circuit allows for the program voltage applied to the control gate of a memory cell to be ramped from a low voltage to a high voltage in a precise manner. The ramp rate of this program voltage is primarily determined by a single capacitor and the bias current provided thereto. By providing a ramped program voltage to the memory array during programming operations, present embodiments effectively cover the entire distribution of program voltage v. program current for the memory cells to be programmed, thereby minimizing over-program and under-program conditions without reducing program time.
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Vikram L Kowshik from Cupertino, CA, age ~70 Get Report