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Vida Vakilotojar

from Mountain View, CA
Age ~58
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Connected to:
Majid Vakilynejad, 61Fariba Vakilzadian, 64Charles K Vakirtzis, 71Dorothea J Vakis, 69Sridevi A Vakkalanka, 46Asher V Vaknin, 52Michal Vaknin, 54Moshe Vaknin, 61Nissim N Vaknin, 63Ortal Vaknin, 41

Vida Vakilotojar Phones & Addresses

  • 226 Central Ave, Mountain View, CA 94043
  • 265 Rengstorff Ave, Mountain View, CA 94043
  • 2124 Rock St, Mountain View, CA 94043
  • 645 23Rd St, Los Angeles, CA 90007
  • Santa Clara, CA
  • Berkeley, CA

Work

Company: Escadapps llc 2013 Position: Founder

Education

School / High School: Stanford University online, Coursera, Udacity 2011 Specialities: Machine Learning, Artificial Intelligence

Skills

Architecture • specification • modeling • and verification of Network Processors • SoC/Multi-Core Server Processor Intercon... • and Cache Hierarchy Architecture. Archit... • modeling • development • and verification of other concurrent sys... • Safety Critical Distributed Systems • MultiUser DataBases. Formal verification... • Abstraction • Partial Order Reduction techniques. Comp... • Robotics • 3D Graphics • DataBases.

Languages

English • Persian

Industries

Computer Software

Resumes

Resumes

Vida Vakilotojar Photo 1

Vida Vakilotojar

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Location:
226 Central Ave, Mountain View, CA 94043
Industry:
Computer Software
Work:
Escadapps
Skills:
Formal Verification
Soc
Distributed Systems
Objective C
Ios Development
Software Design
Algorithms
Deep Learning
Artificial Intelligence
Machine Learning
Robotics
C++
C
User Interface Design
Memory Architecture
Soc Interconnect Architecture
Multicore Server Architecture
Cache Coherency
Asynchronous Systems
Architecture
System Architecture
Model Checking
Tensorflow
Smv
Tla+
Functional Verification
Embedded Software
Cuda
Probabilistic Models
Octave
Python
Languages:
English
Persian
Vida Vakilotojar Photo 2

Vida Vakilotojar Mountain View, CA

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Work:
Escadapps LLC

2013 to 2000
Founder
Intel Corp

2008 to 2011
Enterprise Architect
Sonics Inc

2006 to 2007
Sr. Architect
PMC-Sierra Inc

2000 to 2005
Senior Design Verification Engineer
Cadence Design Systems, Berkeley Labs

1997 to 1997
Summer Intern
www.maharan.com

1991 to 1994
Design Engineer, Project Manager, Consultant
Iran System Corp

1991 to 1991
Software Design Engineer
Education:
Stanford University online, Coursera, Udacity
2011 to 2012
Machine Learning, Artificial Intelligence
University of Southern California
1995 to 2000
Ph.D. in Computer Engineering
Amirkabir University of Technology
1992 to 1995
M.S. in Computer Engineering
Sharif University of Technology
1985 to 1990
B.S. in Electrical Engineering
Skills:
Architecture, specification, modeling, and verification of Network Processors, SoC/Multi-Core Server Processor Interconnect, and Cache Hierarchy Architecture. Architecture, modeling, development, and verification of other concurrent systems: Asynchronous Systems, Safety Critical Distributed Systems, MultiUser DataBases. Formal verification tools development and techniques: Symbolic Model Checking, Abstraction, Partial Order Reduction techniques. Complex algorithm and Object Oriented software design: Formal verification, Robotics, 3D Graphics, DataBases.

Business Records

Name / Title
Company / Classification
Phones & Addresses
Vida Vakilotojar
Escadapps LLC
Custom Computer Programing Computer Systems Design Business Services at Non-Commercial Site
226 Central Ave, Mountain View, CA 94043

Publications

Us Patents

Various Methods And Apparatus For Address Tiling

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US Patent:
8108648, Jan 31, 2012
Filed:
Mar 12, 2009
Appl. No.:
12/402704
Inventors:
Krishnan Srinivasan - Cupertino CA, US
Drew E. Wingard - Palo Alto CA, US
Vida Vakilotojar - Mountain View CA, US
Chien-Chun Chou - Saratoga CA, US
Assignee:
Sonics, Inc. - Milpitas CA
International Classification:
G06F 12/00
US Classification:
711170, 711 5, 711105, 711173, 711202
Abstract:
Various methods and apparatus are described for a memory scheduler. The memory scheduler couples to a target memory core that includes a bank of memories. The memory scheduler contains two or more configurable address tiling functions to transform an incoming address of data requested in a request to the target memory core to determine what physical addresses in the bank of memories will service the first request. The two or more configurable address tiling functions are programmable by a user to create two or more distinctly different memory regions in the target memory core. Each memory region has its own distinct tiling function based on configuration parameters 1) selected by the user and 2) stored in tiling registers in the memory scheduler. The multiple tiling functions are configured to operate concurrently in the integrated circuit.

Interconnect Implementing Internal Controls

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US Patent:
8407433, Mar 26, 2013
Filed:
Jun 24, 2008
Appl. No.:
12/144883
Inventors:
Drew E. Wingard - Palo Alto CA, US
Chien-Chun Chou - Saratoga CA, US
Stephen W. Hamilton - Pembroke Pines FL, US
Ian Andrew Swarbrick - Sunnyvale CA, US
Vida Vakilotojar - Mountain View CA, US
Assignee:
Sonics, Inc. - Milpitas CA
International Classification:
G06F 12/00
US Classification:
711157, 711201
Abstract:
In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect. Two or more memory channels make up a first aggregate target of the target IP cores. The two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop individual two-dimensional (2D) transactions that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more 2D transactions with a height value greater than one, as well as stride and width dimensions, which are chopped to fit within memory channel address boundaries of the first aggregate target.

Apparatus, System, And Methods For Facilitating One-Way Ordering Of Messages

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US Patent:
8554851, Oct 8, 2013
Filed:
Sep 24, 2010
Appl. No.:
12/889802
Inventors:
James R. Vash - Littleton MA, US
Vida Vakilotojar - Mountain View CA, US
Bongjin Jung - Westford MA, US
Yen-Cheng Liu - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 15/16
US Classification:
709206, 709203, 709230, 709223, 709224, 709225, 370389, 370392, 711146, 711141, 711142
Abstract:
Methods, apparatus and systems for facilitating one-way ordering of otherwise independent message classes. A one-way message ordering mechanism facilitates one-way ordering of messages of different message classes sent between interconnects employing independent pathways for the message classes. In one aspect, messages of a second message class may not pass messages of a first message class. Moreover, when messages of the first and second classes are received in sequence, the ordering mechanism ensures that messages of the first class are forwarded to, and received at, a next hop prior to forwarding messages of the second class.

Various Methods And Apparatuses For Cycle Accurate C-Models Of Components

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US Patent:
20080263486, Oct 23, 2008
Filed:
May 19, 2008
Appl. No.:
12/122988
Inventors:
Herve Alexanian - San Jose CA, US
Chien-Chun Chou - Saratoga CA, US
Vida Vakilotojar - Mountain View CA, US
Grigor Yeghiazaryan - Yerevan, AM
Assignee:
Sonics, Inc. - Milpitas CA
International Classification:
G06F 17/50
US Classification:
716 5
Abstract:
Various methods and apparatuses are described for generating a model of hardware components making up an interconnect that facilitates communications between Intellectual Property blocks in an integrated circuit coded in a software programming language at a high level of abstraction that is cycle accurate to a corresponding lower level of abstraction description of the hardware components making up the interconnect. The sub-components of the model at the high level of abstraction are tested in a simulation environment in parallel with the same sub-components of a model coded in a hardware description language at the low level of abstraction in order to verify the functional accuracy and cycle timing between the two models. After the sub-components are tested, the sub-components of the model at the high level of abstraction may be aggregated into a single model at the high level of abstraction that is functionally accurate and cycle accurate to the model at the low level of abstraction.

Various Methods And Apparatus To Support Transactions Whose Data Address Sequence Within That Transaction Crosses An Interleaved Channel Address Boundary

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US Patent:
20080320254, Dec 25, 2008
Filed:
Jun 24, 2008
Appl. No.:
12/145052
Inventors:
Drew E. Wingard - Palo Alto CA, US
Chien-Chun Chou - Saratoga CA, US
Stephen W. Hamilton - Pembroke Pines FL, US
Ian Andrew Swarbrick - Sunnyvale CA, US
Vida Vakilotojar - Mountain View CA, US
Assignee:
Sonics, Inc. - Milpitas CA
International Classification:
G06F 12/06
US Classification:
711157, 711105, 711E12083, 711E12079
Abstract:
A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.

Various Methods And Apparatus For Configurable Mapping Of Address Regions Onto One Or More Aggregate Targets

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US Patent:
20080320255, Dec 25, 2008
Filed:
Jun 24, 2008
Appl. No.:
12/145257
Inventors:
Drew E. Wingard - Palo Alto CA, US
Chien-Chun Chou - Saratoga CA, US
Stephen W. Hamilton - Pembroke Pines FL, US
Ian Andrew Swarbrick - Sunnyvale CA, US
Vida Vakilotojar - Mountain View CA, US
Assignee:
Sonics, Inc. - Milpitas CA
International Classification:
G06F 12/02
US Classification:
711157, 711E12005
Abstract:
An interconnect for an integrated circuit communicating transactions between initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect is generally described. The interconnect routes the transactions between the target IP cores and initiator IP cores in the integrated circuit. A first aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the first aggregate target in the address map. Each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels. An address map is divided up into two or more regions. Each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, and parameters associated with the regions and memory interleave segments are configurable.

Various Methods And Apparatus To Support Outstanding Requests To Multiple Targets While Maintaining Transaction Ordering

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US Patent:
20080320476, Dec 25, 2008
Filed:
Jun 24, 2008
Appl. No.:
12/144987
Inventors:
Drew E. Wingard - Palo Alto CA, US
Chien-Chun Chou - Saratoga CA, US
Stephen W. Hamilton - Pembroke Pines FL, US
Ian Andrew Swarbrick - Sunnyvale CA, US
Vida Vakilotojar - Mountain View CA, US
Assignee:
Sonics, Inc. - Milpitas CA
International Classification:
G06F 9/46
US Classification:
718101
Abstract:
A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect in an integrated circuit communicates transactions between initiator Intellectual Property (IP) cores and target IP cores coupled to the interconnect. The interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions. The logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction and while ensuring an expected execution order within the first transaction and second transaction are maintained. The logic does not include any reorder buffering.

Interconnect That Eliminates Routing Congestion And Manages Simultaneous Transactions

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US Patent:
20120036296, Feb 9, 2012
Filed:
Oct 18, 2011
Appl. No.:
13/276041
Inventors:
Drew E. Wingard - Palo Alto CA, US
Chien-Chun Chou - Saratoga CA, US
Stephen W. Hamilton - Pembroke Pines FL, US
Ian Andrew Swarbrick - Sunnyvale CA, US
Vida Vakilotojar - Mountain View CA, US
Assignee:
SONICS, INC. - Milpitas CA
International Classification:
G06F 13/42
US Classification:
710105
Abstract:
A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect. The flow control logic for the interconnect applies a flow control splitting protocol to permit transactions from each initiator thread and/or each initiator tag stream to be outstanding to multiple channels in a single aggregate target at once, and therefore to multiple individual targets within an aggregate target at once. The combined flow control logic and flow control protocol allows the interconnect to manage simultaneous requests to multiple channels in an aggregate target from the same thread or tag at the same time.
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Vida Vakilotojar from Mountain View, CA, age ~58 Get Report