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Charles K Vakirtzis

from New Windsor, NY
Age ~71
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Related to:
Elsalee J Flynn, 51Eric B Galow, 54Teresa A Galow, 70Joshua P Galow, 34Angelo Dedes, 65Peter Vakirtzis, 98Panayiotis VakirtzisVassiliki K Vakirtzis, 36Grammatiki K Vakirtzis, 32Frances E Vakirtzis, 59Vivian G Dalupan, 83Len Dalupan, 58Adamantios M Vakirtzis, 60Anna M Vakirtzis, 64
Connected to:
Dorothea J Vakis, 69Sridevi A Vakkalanka, 46Asher V Vaknin, 52Michal Vaknin, 54Moshe Vaknin, 61Nissim N Vaknin, 63Ortal Vaknin, 41Ran Y Vaknin, 51Caleb S Vakoc, 27Carolyn K Vakoc, 84

Charles Vakirtzis Phones & Addresses

  • 64 Steele Rd, New Windsor, NY 12553 (845) 565-0086
  • 41 Steele Rd, New Windsor, NY 12553
  • Newburgh, NY
  • Beacon, NY
  • Slate Hill, NY

Work

Company: Ibm 1977 to 2009 Position: Development engineer at ibm

Education

Degree: Bachelors, Bachelor of Science In Electrical Engineering School / High School: Rochester Institute of Technology 1973 to 1975 Specialities: Engineering

Industries

Information Technology And Services

Resumes

Resumes

Charles Vakirtzis Photo 1

Charles Vakirtzis

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Location:
15 Polk Ct, North Potomac, MD 20878
Industry:
Information Technology And Services
Work:
Ibm 1977 - 2009
Development Engineer at Ibm
Education:
Rochester Institute of Technology 1973 - 1975
Bachelors, Bachelor of Science In Electrical Engineering, Engineering Dutchess Community College 1970 - 1973
Associates, Associate of Arts Beacon High School 1967 - 1970

Publications

Us Patents

Method, System, And Computer Program Product For Coupled Noise Timing Violation Avoidance In Detailed Routing

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US Patent:
7904861, Mar 8, 2011
Filed:
Jun 13, 2007
Appl. No.:
11/762130
Inventors:
Markus Buehler - Schonbuch, DE
Moussadek Belaidi - Fishkill NY, US
James J. Curtin - Fishkill NY, US
Adam P. Matheny - Beacon NY, US
Bryan A. Meyer - South Pasadena CA, US
Douglas S. Search - Red Hook NY, US
Dhaval R. Sejpal - Austin TX, US
Charles Vakirtzis - New Windsor NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716108, 716110, 716111, 716112, 716113, 716115, 716126
Abstract:
A method, system, and computer program product for coupled noise timing violation avoidance in detailed routing of an integrated circuit design are provided. The method includes calculating a noise induced timing violation sensitivity (NITVS) metric for nets in the integrated circuit design as a measure of sensitivity to a timing violation relative to a coupled noise delay adder, prioritizing routing isolation as a function of the NITVS metric for each of the nets to avoid coupled noise timing violations, and outputting the routing isolation priority.

Reducing Coupling Between Wires Of An Electronic Circuit

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US Patent:
8006208, Aug 23, 2011
Filed:
May 18, 2010
Appl. No.:
12/781851
Inventors:
Moussadek Belaidi - Fishkill NY, US
Markus Buehler - Schoenbuch, DE
James J. Curtin - Fishkill NY, US
Adam P. Matheny - Beacon NY, US
Bryan A. Meyer - South Pasadena CA, US
Douglas S. Search - Red Hook NY, US
Dhaval R. Sejpal - Austin TX, US
Charles Vakirtzis - New Windsor NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 9/455
US Classification:
716115, 716126
Abstract:
A routing method for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.

Structure For An Integrated Circuit Design For Reducing Coupling Between Wires Of An Electronic Circuit

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US Patent:
8032851, Oct 4, 2011
Filed:
Aug 28, 2007
Appl. No.:
11/845852
Inventors:
Moussadek Belaidi - Fishkill NY, US
Markus Buehler - Weil im Schoenbuch, DE
James J. Curtin - Fishkill NY, US
Adam P. Matheny - Beacon NY, US
Bryan A. Meyer - South Pasadena CA, US
Douglas S. Search - Red Hook NY, US
Dhaval R. Sejpal - Austin TX, US
Charles Vakirtzis - New Windsor NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716115, 716126, 716129, 716130
Abstract:
A design structure for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.

Routing Method For Reducing Coupling Between Wires Of An Electronic Circuit

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US Patent:
20080148213, Jun 19, 2008
Filed:
Aug 27, 2007
Appl. No.:
11/845301
Inventors:
Moussadek Belaidi - Fishkill NY, US
Markus Buehler - Weil im Schoenbuch, DE
James J. Curtin - Fishkill NY, US
Adam P. Matheny - Beacon NY, US
Bryan A. Meyer - South Pasadena CA, US
Douglas S. Search - Red Hook NY, US
Dhaval R. Sejpal - Austin TX, US
Charles Vakirtzis - New Windsor NY, US
International Classification:
G06F 17/50
US Classification:
716 13
Abstract:
A routing method for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.

Early High Level Net Based Analysis Of Simultaneous Switching

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US Patent:
54774608, Dec 19, 1995
Filed:
Dec 21, 1994
Appl. No.:
8/360519
Inventors:
Charles K. Vakirtzis - New Windsor NY
George A. Katopis - Poughkeepsie NY
Gerald W. Mahoney - Poughkeepsie NY
Craig R. Selinger - Spring Valley NY
Bradley D. McCredie - Poughquag NY
Wiren D. Becker - Hyde Park NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1750
US Classification:
364489
Abstract:
Switching characteristics of system components are represented and summed so that their effects on the overall system can be observed during the design process. Full simultaneous switching analysis is provided at the earliest levels of design containing minimal level of design data by a method of computing net based simultaneous switching noise levels which supports packages ranging from the smallest chip level to the largest board level. The simultaneous switching activity is computed based on interaction between each driver and each other driver between each component and each other component, with consideration to the spatial inter-relationship net, within a higher level component, to determine each component's drivers effect on itself as well as the coupling effect between drivers on different components. The analysis involves computing simultaneous switching noise by associating a characteristic triangle with each driver application configuration. The characteristic triangle.

On-Chip Temperature Sensing System

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US Patent:
56391633, Jun 17, 1997
Filed:
Nov 14, 1994
Appl. No.:
8/339056
Inventors:
Evan Ezra Davidson - Hopewell Junction NY
Francis Edward Bosco - Poughkeepsie NY
Charles Kyriakos Vakirtzis - New Windsor NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01K 701
US Classification:
374178
Abstract:
A pair of on-chip thermal sensing diodes are formed together and interconnected with a common cathode to form a differential sensing pair. A pair of precision resistors external to the chip generates two constant currents, one for each diode, with a ratio of one to the other on the order of 100 to 1. The precision resistor values are selected so that variations about the nominal values of metal and via resistances between the diode contacts and the chip contact pads (e. g. C4 contacts) are negligible compared to the precision resistor values. Leads, connected respectively to two pads on the chip, couple a differential output of the anode voltages of the diode pair to the input of a high impedance amplifier.
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Charles K Vakirtzis from New Windsor, NY, age ~71 Get Report