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To D Liang

from Pflugerville, TX
Age ~54
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Also known as:
To Linh Liang, To O Liang, To D Luong, Dieu Liang To, Liang To
Phone and address:
1601 Viki Lynn Ct, Pflugerville, TX 78660
Related to:
Le H NguyenChi Nguyen, 72Huan Nguyen, 51Tina Nguyen, 54Thuy T Nguyen, 62Cuong Nguyen, 50
Connected to:
A Liang, 66Abby Liang, 103Alyssa Liang, 28Andy Y Liang, 47Audrey Y Liang, 29Bernice H Liang, 58Billy C Liang, 46Bo Liang, 53Caroline Liang, 31Casey Z Liang, 40

To Liang Phones & Addresses

  • 1601 Viki Lynn Ct, Pflugerville, TX 78660
  • Round Rock, TX
  • Milpitas, CA
  • Austin, TX
  • Travis, TX

Work

Company: Ibm 2008 to Apr 2010 Position: Powerpc bring up and validation

Education

Degree: Bachelor of Science School / High School: The University of Texas at Austin 1990 to 1995 Specialities: Electrical Engineering

Skills

Debugging • Embedded Systems • Perl • Functional Verification • Asic

Industries

Computer Hardware

Resumes

Resumes

To Liang Photo 1

To Liang

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Location:
Round Rock, TX
Industry:
Computer Hardware
Work:
IBM 2008 - Apr 2010
PowerPC Bring up and Validation
IBM Aug 2000 - 2008
HW Validation Engineer
Motorola 1998 - 2000
Product & Test Engineer
National Semiconductor 1996 - 1998
Test Development Engineer
Education:
The University of Texas at Austin 1990 - 1995
Bachelor of Science, Electrical Engineering
Skills:
Debugging
Embedded Systems
Perl
Functional Verification
Asic

Publications

Us Patents

Method And Apparatus For Characterizing Components Of A Device Under Test Using On-Chip Trace Logic Analyzer

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US Patent:
20080028269, Jan 31, 2008
Filed:
Jul 27, 2006
Appl. No.:
11/460471
Inventors:
KERRY CHRISTOPHER IMMING - ROCHESTER MN, US
RESHAM RAJENDRA KULKARNI - AUSTIN TX, US
TO DIEU LIANG - ROUND ROCK TX, US
SARAH SABRA PETTENGILL - AUSTIN TX, US
Assignee:
IBM Corporation - Austin TX
International Classification:
G01R 31/28
US Classification:
714738
Abstract:
A test system is disclosed wherein a device under test (DUT) includes a trace logic analyzer (TLA) that receives and stores test data. The test system includes both a master tester and a slave tester. The slave tester operates at a high speed data rate substantially faster than that of the master tester. The master tester instructs the TLA to monitor data that the DUT receives from the slave tester to detect a predetermined data pattern within the data. The slave tester transmits data including the predetermined data pattern to the DUT. The DUT receives the data. When the TLA in the DUT detects the predetermined data pattern in the received data, the TLA stores that data pattern as a stored data pattern. The master tester retrieves the stored data pattern and compares the stored data pattern with the original predetermined data pattern. If the master tester determines that the stored data pattern is the same as the original predetermined data pattern, then the master tester generates a pass result. Otherwise, the master tester generates a fail result. In one embodiment, the DUT includes multiple receivers and the system determines a pass/fail rating on a per receiver basis.
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To D Liang from Pflugerville, TX, age ~54 Get Report