Resumes
Resumes
Swaroop Raghunatha Phones & Addresses
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Lathrop, CA
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Mountain House, CA
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Gainesville, GA
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952 Cameron Cir, Milpitas, CA 95035 (408) 942-1185
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3760 Tamarack Ln, Santa Clara, CA 95051 (408) 247-9665
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952 Cameron Cir, Milpitas, CA 95035 (408) 497-8756
Work
Position:
Professional/Technical
Education
Degree:
Graduate or professional degree
Emails
Publications
Us Patents
Temporal Alignment Of Data Unit Groups In A Switch
View pageUS Patent:
8300479, Oct 30, 2012
Filed:
Mar 25, 2010
Appl. No.:
12/731948
Inventors:
Chung Kuang Chin - Saratoga CA, US
Edward E. Sprague - Woodside CA, US
Prasad Paranjape - Fremont CA, US
Swaroop Raghunatha - Milpitas CA, US
Venkat Talapaneni - Cupertino CA, US
Edward E. Sprague - Woodside CA, US
Prasad Paranjape - Fremont CA, US
Swaroop Raghunatha - Milpitas CA, US
Venkat Talapaneni - Cupertino CA, US
Assignee:
Infinera Corporation - Sunnyvale CA
International Classification:
G11C 7/00
G11C 8/00
G11C 8/00
US Classification:
36518905, 36518917, 365194, 36523003, 36523005, 3652331
Abstract:
Consistent with the present disclosure, a plurality of FIFO buffers, for example, are provided in a switch, which also includes a switch fabric. Each of the plurality of FIFOs is pre-filled with data for a duration based on a skew or time difference between the time that a data unit group is supplied to its corresponding FIFO and a reference time. The reference time is the time, for example, after a delay period has lapsed following the leading edge of a synch signal, the timing of which is a known system parameter and is used to trigger switching in the switch fabric. Typically, the delay period may be equal to the latency (often, another known system parameter) or length of time required for the data unit to propagate from an input circuit, such as a line card of the switch or another switch, to the FIFO that receives the data unit. At the reference time, temporally aligned data unit groups may be read or output from each FIFO and supplied to the switch fabric. Since the timing of the output from the FIFOs is based on known system parameters, instead of the actual arrival of the slowest data unit group at its corresponding FIFO, time aligned data unit groups may be output regardless of whether the slowest data unit group is available.
Interleaved Correction Code Transmission
View pageUS Patent:
8370706, Feb 5, 2013
Filed:
Oct 2, 2009
Appl. No.:
12/572422
Inventors:
Chung Kuang Chin - Saratoga CA, US
Edward E. Sprague - Woodside CA, US
Swaroop Raghunatha - Milpitas CA, US
Edward E. Sprague - Woodside CA, US
Swaroop Raghunatha - Milpitas CA, US
Assignee:
Infinera Corporation - Sunnyvale CA
International Classification:
H03M 13/00
H03M 13/03
G06F 11/00
H04B 3/46
H03M 13/03
G06F 11/00
H04B 3/46
US Classification:
714758, 714757, 714784, 714752, 714786, 714821, 370216, 370241, 370242, 375224
Abstract:
An optical device transmits ECC codewords using an interleaved technique in which a single ECC codeword is transmitted over multiple optical links. In one particular implementation, the device may include an ECC circuit configured to supply ECC codewords in series, the codewords being generated by the ECC circuit based on input data and each of the codewords including error correction information and a portion of the data. The device may further include a serial-to-parallel circuit configured to receive each of the codewords in succession, and supply data units in parallel, each of the data units including information from a corresponding one of the codewords; an interleaver circuit to receive the data units in parallel and output a second data units in parallel, each of the second data units including bits from different ones of the data units; and a number of output lines, each of which supplying a corresponding one of the second data units.
Simultaneous Switching Of Multiple Time Slots In An Optical Network Node
View pageUS Patent:
20110055491, Mar 3, 2011
Filed:
Aug 31, 2009
Appl. No.:
12/550497
Inventors:
Chung Kuang Chin - Saratoga CA, US
Shankar Venkataraman - Sunnyvale CA, US
Swaroop Raghunatha - Milpitas CA, US
Shankar Venkataraman - Sunnyvale CA, US
Swaroop Raghunatha - Milpitas CA, US
International Classification:
G06F 12/00
US Classification:
711149, 711E12001
Abstract:
A switching frame buffer is described in which data units within a sequence of time slots, of a frame, may be simultaneously input and output at ports of the switching frame buffer. In one implementation, a write port may receive data units within a single cycle of the switch. A number of memories may be provided, where first selected ones of the memories constitute memory groups and second selected ones of the memories constitute a memory subsets, each of the memory groups including a corresponding one of the memory subsets. The write port may supply each of a number of copies of the data units to a corresponding one of the memory subsets. Multiplexers may be associated with the groups of the memories and a read port may receive one of the copies of a number of the data units from different ones of the multiplexers.