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Samyukta K Mudugal

from Erie, CO
Age ~38

Samyukta Mudugal Phones & Addresses

  • 1540 Meachum Way, Erie, CO 80516
  • Boulder, CO
  • Colorado Springs, CO
  • Denver, CO

Work

Company: Lsi corporation May 2011 Position: Firmware develpoment engineer

Education

Degree: MS School / High School: University of Colorado at Boulder 2009 to 2011 Specialities: ECEE

Skills

C • C++ • Storage • Embedded Software • Nvme • Firmware • Solid State Drive • Embedded Systems • Debugging • Sas • Raid • Microcontrollers • Testing • Digital Signal Processors • Programming • Python • Fpga • Clearquest • Clearcase

Languages

English

Industries

Semiconductors

Resumes

Resumes

Samyukta Mudugal Photo 1

Senior Firmware Engineer

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Location:
Boulder, CO
Industry:
Semiconductors
Work:
LSI Corporation since May 2011
Firmware Develpoment Engineer

Covidien May 2010 - Apr 2011
R&D Intern

University of Colorado at Boulder Aug 2010 - Dec 2010
Grader - Circuits for Mechanical Engineers

University of Colorado at Boulder Jan 2010 - Aug 2010
Tutor
Education:
University of Colorado at Boulder 2009 - 2011
MS, ECEE
B. M. S. College of Engineering 2005 - 2009
Bachelor of Engineering (BE), Electrical, Electronics and Communications Engineering
Skills:
C
C++
Storage
Embedded Software
Nvme
Firmware
Solid State Drive
Embedded Systems
Debugging
Sas
Raid
Microcontrollers
Testing
Digital Signal Processors
Programming
Python
Fpga
Clearquest
Clearcase
Languages:
English

Publications

Us Patents

Virtual Management Unit Scheme For Two-Pass Programming In A Memory Sub-System

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US Patent:
20230061180, Mar 2, 2023
Filed:
Sep 1, 2021
Appl. No.:
17/464442
Inventors:
- Boise ID, US
Samyukta Mudugal - Erie CO, US
Sanjay Subbarao - Irvine CA, US
Byron D. Harris - Mead CO, US
Daniel A. Boals - Broomfield CO, US
International Classification:
G06F 3/06
Abstract:
A data item is programmed to a first set of management units (MUs) associated with a first portion of one or more memory devices. The first portion includes memory cells of a first type. The first set of MUs is associated with a first physical address. A mapping is generated in a virtual MU data structure that associates the first physical address with a set of virtual MUs associated with the one or more memory devices. An entry associated with the data item is added to a logical-to-physical (L2P) table associated with the one or more memory devices. The entry includes an identifier associated with the set of virtual MUs associated with the one or more memory devices. A detection is made that the data item is programmed to a second set of MUs associated with a second portion of the one or more memory devices. The second portion includes memory cells of a second type. The second set of MUs is associated with a second physical address. The mapping is updated to associate the set of virtual MUs with the second physical address.
Samyukta K Mudugal from Erie, CO, age ~38 Get Report