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Pavan Kumar Mudunuru

from Acton, MA
Age ~42
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Also known as:
Pavan K Mudunuru, Pavan Kuma Mudunuru, Pavan C Mudunuru, Chandra S Mudunuru, Pavankumar C Mudunuru, Pavan Kumar
Connected to:
Praveen N Mudunuri, 39Swarna L Mudunuri, 43Ambar A Mudur, 54Shyla S Mudur, 52Ciprian Mudura, 39Cassidy Mudurian, 44Stacey D Muduryan, 53Edward J Mueck, 43Katelyn Mueck, 33Melissa J Mueck, 53

Pavan Mudunuru Phones & Addresses

  • Acton, MA
  • Lowell, MA
  • Hudson, MA
  • Sharon, MA
  • Shrewsbury, MA
  • Waltham, MA
  • Malden, MA
  • Sunnyvale, CA
  • Belmont, CA
  • Kearny, NJ
  • New York, NY
  • Chestnut Hill, MA
  • 647 Massapoag Ave, Sharon, MA 02067

Resumes

Resumes

Pavan Mudunuru Photo 1

Senior Design Manager

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Location:
P/O Box 156, Wellsville, UT
Industry:
Semiconductors
Work:
Autoliv - Lowell, MA since Apr 2010
Hardware Design Engineer
Sensata Technologies May 2007 - Apr 2009
Sr. Design Engineer
Cypress Semiconductor Dec 2004 - May 2007
Sr. Design Engineer
National Semiconductor Corporation Jun 2004 - Dec 2004
CAD Coop Engineer
Education:
Massachusetts Institute of Technology 2005 - 2005
Southern Illinois University, Carbondale 2002 - 2004
M.S., Electrical and Computer Engineering Sreenidhi Institute of Science and Technology 1998 - 2002
Bachelors in Science, Electrical and Computer Engineering
Skills:
Analog Circuit Design
Embedded Systems
Ic
Mixed Signal
Hardware Architecture
Sensors
Digital Signal Processors
Cmos
Pcb Design
Semiconductors
Microcontrollers
Debugging
Simulations
Vlsi
Verilog
Asic
Manufacturing
Pll
I2C
Microprocessors
Languages:
Hindi
Telugu
Pavan Mudunuru Photo 2

Hardware Design Engineer At Autoliv

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Position:
Hardware Design Engineer at Autoliv
Location:
Greater Boston Area
Industry:
Semiconductors
Work:
Autoliv - Lowell, MA since Apr 2010
Hardware Design Engineer
Sensata Technologies May 2007 - Apr 2009
Sr. Design Engineer
Cypress Semiconductor Dec 2004 - May 2007
Sr. Design Engineer
National Semiconductor Corporation Jun 2004 - Dec 2004
CAD Coop Engineer
Education:
Massachusetts Institute of Technology 2005 - 2005
Southern Illinois University, Carbondale 2002 - 2004
M.S., Electrical and Computer Engineering Sreenidhi Institute of Science and Technology 1998 - 2002
Bachelors in Science, Electrical and Computer Engineering
Skills:
Embedded Systems
Analog Circuit Design
VLSI
Verilog
Mixed Signal
Semiconductors
ASIC
Digital Signal Processors
Microcontrollers
IC
Debugging
Hardware Architecture
Sensors
I2C
Microprocessors
CMOS
PCB design
PLL
Simulations
Languages:
Hindi
Telugu

Publications

Us Patents

Sequence Independent Non-Overlapping Digital Signal Generator With Programmable Delay

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US Patent:
20080224743, Sep 18, 2008
Filed:
Sep 17, 2007
Appl. No.:
11/856301
Inventors:
Jungwook Yang - Newton MA, US
Lane Brooks - Highland UT, US
Pavan Mudunuru - Malden MA, US
International Classification:
H03L 7/00
US Classification:
327153
Abstract:
A circuit for generating non-overlapping clock signals includes a programmable delayed reference clock signals circuit to produce a plurality of delayed reference clock signals and a plurality of delay clock signal generators, operatively connected to the programmable delayed reference clock signals circuit, to generate non-overlapping clock signals. Each delay clock signal generator includes a latch or flip-flop to control a delay in a rising edge of a clock signal and to output a first signal, another latch or flip-flop to control a delay in a falling edge of a delayed clock signal and to output a first signal, and a logic circuit to generate the clock signal from the first and second signals. The latches or flip-flops independently control a delay in the rising edge of the clock signal in response to one of the plurality of delayed reference clock signals.
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Pavan Kumar Mudunuru from Acton, MA, age ~42 Get Report