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Robert J Yagley

from Lexington, KY
Deceased
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Related to:
Andres ThomasRegis G Tologo, 70Martin J Thomas, 75Matthew Yagley, 40John A MarecekLaura K Bennett, 42Ivonne K Yagley, 59
Connected to:
Kristen Yagley, 34Yvonne Yaglosky, 54Tyler C Yagman, 34Prashant Yagnavajhala, 51Bob Yagnich, 84Anant M Yagnik, 49Gargey B Yagnik, 44Gunjan Yagnik, 32Khyati B Yagnik, 41Manisha D Yagnik, 56

Robert Yagley Phones & Addresses

  • 2902 Azov Ct, Lexington, KY 40503 (859) 278-3915
  • 2909 Azov Ct, Lexington, KY 40503 (859) 278-3915
  • Endicott, NY
  • Cary, NC
  • Winterville, NC

Publications

Us Patents

Efficient, Flexible Motion Estimation Architecture For Real Time Mpeg2 Compliant Encoding

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US Patent:
6549575, Apr 15, 2003
Filed:
Nov 7, 1996
Appl. No.:
08/745584
Inventors:
Adrian Stephen Butter - Binghamton NY
John Mark Kaczmarczyk - Endicott NY
Agnes Yee Ngai - Endwell NY
Edward Francis Westermann - Endicott NY
Robert J. Yagley - Endicott NY
Assignee:
International Business Machines Corporation. - Armonk NY
International Classification:
H04N 732
US Classification:
37524016
Abstract:
Temporal compression of a digital video data stream with hierarchically searching in at least one search unit for pixels in a reference picture to find a best match for the current macroblock. This is followed by constructing a motion vector between the current macroblock and the best match macroblock in the reference picture.

Scalable Mpeg2 Compliant Video Encoder

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US Patent:
57685371, Jun 16, 1998
Filed:
Feb 22, 1996
Appl. No.:
8/605559
Inventors:
Adrian Stephen Butter - Binghamton NY
John Mark Kaczmarczyk - Endicott NY
Agnes Yee Ngai - Endwell NY
Robert J. Yagley - Endicott NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04N 730
H04N 732
H04N 750
US Classification:
39520077
Abstract:
A scalable architecture MPEG2 compliant digital video encoder system having an I-frame only video encoder module with a Discrete Cosine Transform processor, a quantization unit, a variable length encoder, a FIFO buffer, and a compressed store interface, for generating an I-frame containing bitstream. For IPB bitstreams the system includes a second processor element with a reference memory interface, motion estimation and compensation capability, inverse quantization, and inverse discrete cosine transformation, and motion compensation means; and at least one third processor element motion estimation. The system can be in the form of a single integrated circuit chip, or a plurality of integrated circuit chips, that is one for each processor, the I-frame video encoder module, the second processor element, and the third processor element. There can be one or more of the third processor units.

System And Method For Improving The Integrity Of Control Information

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US Patent:
52854566, Feb 8, 1994
Filed:
May 15, 1991
Appl. No.:
7/700737
Inventors:
Dennis P. Cheney - Vestal NY
Richard C. Lang - Endwell NY
Andrew E. Petruski - Endicott NY
Mark J. Wolski - Vestal NY
Robert J. Yagley - Endicott NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1110
H03M 1300
US Classification:
371 491
Abstract:
A system and method for verifying the integrity of control information and informational data. One embodiment of the present invention verifies the integrity of control information received from a host computer, and verifies the integrity of this information as it is transmitted throughout the present invention. Another embodiment of the present invention contemplates verifying the integrity of informational data sent from a host computer, verifying the integrity of informational data as it is transmitted throughout the present invention, generating a CRC based upon the informational data and control information, and transmitting the informational data, control information and corresponding CRC to a storage device.

Data Storage Buffer System And Method

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US Patent:
52768082, Jan 4, 1994
Filed:
Feb 4, 1991
Appl. No.:
7/650566
Inventors:
Dennis P. Cheney - Vestal NY
Robert J. Yagley - Endicott NY
Mark J. Wolski - Vestal NY
Andrew E. Petruski - Endicott NY
Josephine A. Boston - Wappingers Falls NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1338
G06F 1202
US Classification:
395250
Abstract:
A system and method for striping data to multiple storage devices is provided. One embodiment of the present invention sequentially gates data to a plurality of buffers, wherein only those buffers corresponding to storage devices in use are induced to gate in data. The data is then sent to the storage devices in parallel. Other embodiments further include the use of striping buffers alternatingly used to gate in data, and transfer data to the storage devices.

Data Transfer Bus System And Method Serving Multiple Parallel Asynchronous Units

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US Patent:
53333012, Jul 26, 1994
Filed:
Dec 14, 1990
Appl. No.:
7/626706
Inventors:
Dennis P. Cheney - Vestal NY
James N. Dieffenderfer - Endicott NY
Ronald A. Oreshan - Tucson AZ
Robert J. Yagley - Endicott NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1342
G06F 1110
US Classification:
395575
Abstract:
A system and method for transferring data between a single channel unit and multiple asynchronous storage devices. One embodiment of the present invention uses read strobe signals to indicate when the storage devices are to send data over a data bus, and to initiate a validity count-down which indicates when the data on the data bus is valid. When the count-down has completed, the data on the data bus is sampled. Another embodiment further includes checking the data for array parity errors while the data is sent and received to and from the storage devices.
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Robert J Yagley from Lexington, KYDeceased Get Report