Robert T Rozbicki

6440854, Aug 27, 2002

Feb 2, 2001

09/776702

Robert T. Rozbicki - San Jose CA

Novellus Systems, Inc. - San Jose CA

H01L 2144

438687, 438625, 438628, 438642, 438644, 438650, 438654, 438655, 438658, 438686, 420490, 420497

The present invention pertains to systems and methods for reducing the agglomeration of copper deposited by physical vapor deposition. More specifically, the invention pertains to systems and methods for depositing copper seed layers on a semiconductor wafer. The invention involves the use of an anti-agglomeration agent, so that the copper deposition is completed in an even, continuous and conformal manner.

6554914, Apr 29, 2003

Feb 2, 2001

09/776704

Robert T. Rozbicki - San Jose CA
Ronald Allan Powell - San Carlos CA
Erich Klawuhn - San Jose CA
Michal Danek - Sunnyvale CA
Karl B. Levy - Los Altos CA
Jonathan David Reid - Sherwood OR
Mukul Khosla - San Jose CA
Eliot K. Broadbent - Beaverton OR

Novellus Systems, Inc. - San Jose CA

C23C 824

148238, 148282

The present invention pertains to systems and methods for passivating the copper seed layer deposited in Damascene integrated circuit manufacturing. More specifically, the invention pertains to systems and methods for depositing the copper seed layer by physical vapor deposition, while passivating the copper during or immediately after the deposition in order to prevent excessive oxidation of the copper. The invention is applicable to dual Damascene processing.

6607977, Aug 19, 2003

Sep 26, 2001

09/965472

Robert Rozbicki - San Jose CA
Michal Danek - Cupertino CA
Erich Klawuhn - San Jose CA

Novellus Systems, Inc. - San Jose CA

H01L 214763

438627, 438597, 438622, 438625, 438672, 438687, 438643, 438653

The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit wherein the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the side walls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.

6642146, Nov 4, 2003

Apr 10, 2002

10/121949

Robert Rozbicki - San Francisco CA
Michal Danek - Cupertino CA
Erich Klawuhn - San Jose CA

Novellus Systems, Inc. - San Jose CA

H01L 2144

438687, 438622, 438624, 438625, 438627, 438628, 438629, 438637, 438638, 438644, 438648, 438654, 438656, 438666, 438668, 438672, 438675, 438678, 438685

The present invention pertains to methods for depositing a metal seed layer on a wafer substrate having a plurality of recessed features. Methods of the invention include at least two operations. A first portion of a seed layer is deposited such that metal ions impinge on the wafer substrate substantially perpendicular to the wafer substrate work surface. The first portion is characterized by heavy bottom coverage in the recessed features and minimal overhang on the apertures of the recessed features. A second portion of the metal seed layer is deposited with simultaneous re-sputter of at least part of the first portion that covers the bottom of the features. During re-sputter, part of the seed material on the bottom is redistributed to the sidewalls of the features. Seed layers of the invention have minimal overhang and excellent step coverage.

6764940, Jul 20, 2004

Apr 11, 2003

10/412562

Robert Rozbicki - San Francisco CA
Michal Danek - Cupertino CA

Novellus Systems, Inc. - San Jose CA

H01L 214763

438627, 438637, 438638, 438643, 438653, 438687, 438700, 438720

Methods for forming a metal diffusion barrier on an integrated circuit include at least four operations. The first operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The third operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage especially over the bottoms of unlanded vias. The forth operation deposits a metal conductive layer. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects. In addition, techniques to protect the bottoms of the unlanded vias are described.

7186648, Mar 6, 2007

Mar 18, 2004

10/804353

Robert Rozbicki - San Francisco CA, US
Michal Danek - Cupertino CA, US

Novellus Systems, Inc. - San Jose CA

H01L 21/44

438687, 257E2301

Methods for forming a diffusion barrier on low aspect features of an integrated circuit include at least three operations. The first operation deposits a barrier material and simultaneously etches a portion of an underlying metal at the bottoms of recessed features of the integrated circuit. The second operation deposits barrier material to provide some minimal coverage over the bottoms of the recessed features. The third operation deposits a metal conductive layer. Controlled etching is used to selectively remove barrier material from the bottom of the recessed features, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.

7510634, Mar 31, 2009

Nov 10, 2006

11/558693

Erich R. Klawuhn - Los Altos CA, US
Robert Rozbicki - San Francisco CA, US
Girish A. Dixit - San Jose CA, US

Novellus Systems, Inc. - San Jose CA

C23C 14/35

20429803, 20429816, 20429817, 20429818, 20429823, 20429829, 20419217

Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer. That is, deposition coverage in the bottom of each via of a semiconductor wafer differs from the coverage in the bottom of each trench of such wafer. The selectivity may be configured so as to result in punch through in each via without damaging the dielectric material at the bottom of each trench or the like. In this configuration, the coverage amount deposited in each trench is greater than the coverage amount deposited in each via.

7682966, Mar 23, 2010

Feb 1, 2007

11/701984

Robert Rozbicki - San Francisco CA, US
Bart van Schravendijk - Sunnyvale CA, US
Tom Mountsier - San Jose CA, US
Wen Wu - San Jose CA, US

Novellus Systems, Inc. - San Jose CA

H01L 23/535

438637, 438675, 438687, 257E21169, 257E21175

Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves at least three operations. In this method, a first layer of metal is deposited onto the substrate to cover at least the bottom portions of the recessed features. The first layer of metal is subsequently redistributed to improve sidewall coverage of the recessed features. Next, a second layer of metal is deposited on at least the field region of the substrate and on the bottom portions of the recessed features. The method can be implemented using a PVD apparatus that allows deposition and resputtering operations. This sequence of operations can afford seed layers with improved step coverage. It also leads to decreased formation of voids in interconnects, and to improved resistance characteristics of formed IC devices.