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Rajesh Koul

from San Jose, CA
Age ~55
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Related to:
Annamica Bhan, 52
Connected to:
Avinash Koul, 51Deepika Koul, 51Siddharth Koul, 29Supriya Koul, 39Vipen K Koul, 58Michael A Koulalis, 77Bradley Koulback, 38James E Koulback, 60Moussa A Koulbou, 50Azar Koulibaly, 42

Rajesh Koul Phones & Addresses

  • 1344 Via De Los Reyes, San Jose, CA 95120 (408) 997-7982
  • 4300 The Woods Dr, San Jose, CA 95136 (408) 578-4730
  • 6661 Tradition Ct, San Jose, CA 95120 (408) 997-7982
  • Rochester, MN
  • 1344 Via De Los Reyes, San Jose, CA 95120

Work

Position: Professional/Technical

Education

Degree: Associate degree or higher

Resumes

Resumes

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Technologist

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Location:
San Francisco, CA
Industry:
Computer Hardware
Work:
Ibm May 1999 - May 2012
Principal Engineer
Western Digital May 1999 - May 2012
Technologist
Skills:
Cross Functional Team Leadership
Leadership
Product Development
Embedded Systems
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Rajesh Koul

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Publications

Us Patents

Error Detection And Correction For Encoded Data

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US Patent:
20070011598, Jan 11, 2007
Filed:
Jun 15, 2005
Appl. No.:
11/154978
Inventors:
Martin Hassner - Mountain View CA, US
Rajesh Koul - San Jose CA, US
Assignee:
Hitachi Global Storage Technologies Netherlands B.V. - Amsterdam
International Classification:
G06F 11/00
H03M 13/00
US Classification:
714801000
Abstract:
Embodiments of the present invention provide techniques for detecting and correcting encoded data. In one embodiment, a system for detecting and correcting errors in a plurality of data bits comprises a static memory configured to store a plurality of data bits; a systematic encoder configured to convert the plurality of data bits into a codeword; a systematic parity check encoder configured to convert the codeword into a syndrome; and a syndrome decoder configured to evaluate the syndrome based on preset criteria used to determine whether the syndrome corresponds to an uncorrectable error. A binary [16, 8, 5] code is used to encode the plurality of data bits.

System And Method For Qos Over Nvme Virtualization Platform Using Adaptive Command Fetching

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US Patent:
20190146684, May 16, 2019
Filed:
Nov 13, 2017
Appl. No.:
15/810632
Inventors:
- San Jose CA, US
James Walsh - Santa Clara CA, US
Rajesh Koul - San Jose CA, US
Assignee:
Western Digital Technologies, Inc. - San Jose CA
International Classification:
G06F 3/06
G06F 13/42
Abstract:
Systems and methods for quality of service (QoS) using adaptive command fetching are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device processes the commands through various phases including fetching, processing, posting a completion message, and sending an interrupt to the host. NVMe also includes an NVMe virtualization environment, which uses a subsystem with multiple controllers to provide virtual or physical hosts direct I/O access. QoS may be used so that the NVMe processes in the virtualization environment receive sufficient resources. In particular, bandwidth assigned to a submission queue may be considered when processing of commands (such as fetching of commands). In the event that the bandwidth assigned to the submission queue is exceeded, the processing of the commands (such as the fetching of the commands) may be delayed.

Systems, Methods, And Computer-Readable Media For Managing Instruction Fetch In Virtual Computing Environments

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US Patent:
20180217951, Aug 2, 2018
Filed:
Mar 26, 2018
Appl. No.:
15/936364
Inventors:
- Plano TX, US
Rajesh Koul - San Jose CA, US
International Classification:
G06F 13/16
Abstract:
Methods, systems, and computer readable media for intelligent fetching of storage device commands from submission queues are disclosed. The controller may implement a hierarchical scheme comprising first-level arbitration(s) between submission queues of each of a plurality of input/output virtualization (IOV) functions, and a second-level arbitration between the respective IOV functions. Alternatively, or in addition, the controller may implement a flat arbitration scheme, which may comprise selecting submission queue(s) from one or more groups, each group comprising submission queues of each of the plurality of IOV functions. In some embodiments, the controller implements a credit-based arbitration scheme. The arbitration scheme(s) may be modified in accordance with command statistics and/or current resource availability.

Emergency Power Off (Epo) Island For Saving Critical Data To Non-Volatile Memory

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US Patent:
20140160595, Jun 12, 2014
Filed:
Dec 7, 2012
Appl. No.:
13/708901
Inventors:
- Amsterdam, NL
RAJESH KOUL - SAN JOSE CA, US
RYAN MATTHEW SCHULZ - SAN JOSE CA, US
ANTHONY EDWIN WELTER - ROCHESTER MN, US
Assignee:
HGST NETHERLANDS B.V. - Amsterdam
International Classification:
G11B 19/20
US Classification:
360 9908
Abstract:
Approaches for an emergency power off (EPO) power island, for saving critical data to non-volatile memory in the event of an EPO condition, for use in a hard-disk drive (HDD) storage device. The EPO power island includes a controller for detecting an EPO condition. A voltage regulator supplies power from spindle motor back EMF only to the EPO power island and to the non-volatile memory. Thus, the remainder of the hard drive controller (HDC) is isolated from the EPO power island so that it will not corrupt the data as the HDC's power supply is decaying. Using the power provided by the voltage regulator, the EPO power island transfers critical data from a memory internal to the island to a non-volatile memory external to the island, such as to a flash memory chip.
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Rajesh Koul from San Jose, CA, age ~55 Get Report