Prashantha Kalluraya

7139965, Nov 21, 2006

Oct 8, 2003

10/680884

Paras A. Shah - Houston TX, US
Prashantha Kalluraya - Houston TX, US

Hewlett-Packard Development Company, L.P. - Houston TX

H03M 13/00

714775, 714701

A bus device comprises a clock generator that is adapted to generate a clock signal for internal use by the bus device, data synchronizing logic that is adapted to synchronize source synchronous data that the bus device receives from the bus to the bus device's clock signal, and error detection and correction logic coupled to the data synchronizing logic. The error detection and correction logic is adapted to detect and correct errors associated with the data received from the bus concurrently while the data synchronizing logic synchronizes source synchronous data received from the bus to the clock signal.

20030126491, Jul 3, 2003

Dec 31, 2001

10/038942

Paras Shah - Houston TX, US
Prashantha Kalluraya - Houston TX, US

G06F001/04

713/600000

An application specific integrated circuit (ASIC) employs various logic blocks. The blocks may include logic circuits that operate at different clock rates. Consequently, an interface logic block may be needed to efficiently transfer signals from one frequency clock domain to another. One such interface, known as a universal asynchronous boundary module (UABM) is situated between the two domains allowing communication between the logic circuits.