Seshagiri Prasad Kalluri

6973630, Dec 6, 2005

Apr 7, 2003

10/408387

Tuan Dao - Richardson TX, US
Seshagiri P. Kalluri - Richardson TX, US
Shannon A. Wichman - McKinney TX, US

LSI Logic Corporation - Milpitas CA

G06F017/50

716 1, 716 4

A system for, and method of, reference-modeling a processor design. In one embodiment, the system includes: (1) an architecture database that contains specifications regarding the processor design that include: instruction set specifications, architectural resource specifications, pipeline specifications and connectivity specifications, (2) a simulation subsystem that draws selected portions of the specifications to simulate and test the processor design and (3) a documentation subsystem that draws other selected portions of the specifications to document and register-model the processor design, changes in the specifications being propagated to the architecture database.

7299343, Nov 20, 2007

Sep 27, 2002

10/256864

Seshagiri P. Kalluri - Richardson TX, US
Ramon C. Trombetta - Garland TX, US
Adam C. Krolnik - Allen TX, US

VeriSilicon Holdings (Cayman Islands) Co. Ltd. - Santa Clara CA

G06F 9/44

712226

A system for conditionally executing an instruction depending on a previously existing condition. The system disclosed is configured to handle conditional execution instructions typically specifying at least one target instruction, a processor register, and a condition within the register. The system saves a result of each of the target instructions dependent upon the existence of the condition in the specified register during execution of the conditional execution instruction. When the conditional execution instruction specifies a first flag register, the system copies the flag bits in the first flag register to a corresponding second flag register, and saves a result of each of the target instructions dependent upon the specified condition in the first flag register during execution of the conditional execution instruction. A subsequent conditional execution instruction may then specify a condition in the second flag register in order to conditionally execute target instructions based on a previously existing condition.

7434036, Oct 7, 2008

Aug 30, 2002

10/231948

Shannon A. Wichman - McKinney TX, US
Seshagiri Prasad Kalluri - Richardson TX, US

VeriSilicon Holdings Co. Ltd. - Santa Clara CA

G06F 9/30

712234

A processor is disclosed including an instruction unit and an execution unit. The instruction unit fetches and decodes instructions, including a conditional execution instruction. The conditional execution instruction specifies one or more instructions to be conditionally executed (i. e. , “target instructions”), a register of the processor, and a condition within the register. When the instruction unit fetches and decodes the conditional execution instruction, the execution unit saves results of the one or more target instructions dependent upon the existence of the specified condition in the specified register during execution of the conditional execution instruction. A system including the processor is described, as is a method for conditionally executing at least one instruction.

7607057, Oct 20, 2009

Dec 28, 2004

11/023731

Mark Allen Boike - Plano TX, US
Seshagiri Prasad Kalluri - Richardson TX, US
Vijayanand J. Angarai - Richardson TX, US
David Mark Brantley - Flower Mound TX, US
Scott Avery Beeker - Coppell TX, US

LSI Corporation - Milpitas CA

G01R 31/28

714727, 714 30, 714724, 714729, 716 4

An apparatus and method are disclosed for testing a hard macro that is embedded in a system on a chip (SOC) that is included in an integrated circuit chip. The SOC includes the hard macro. A logic design and operation of the hard macro are unknown. A test wrapper is embedded in the SOC. The test wrapper includes a scan chain. The test wrapper surrounds inputs and outputs of the hard macro. The test wrapper receives a known test data pattern in the scan chain that is included in the test wrapper. The hard macro receives from the test wrapper a set of non-test standard SOC inputs when the SOC is not in a test mode and receives the known test data pattern when the SOC is in the test mode. The hard macro generates a set of outputs in response to the inputs. The hard macro is tested utilizing the known test data pattern.

8516605, Aug 20, 2013

Aug 8, 2007

11/835509

Seshagiri Prasad Kalluri - Richardson TX, US
Danny W. Wilson - Garland TX, US
Adam Christopher Krolnik - Allen TX, US

Verisilicon Holdings Co., Ltd. - Santa Clara CA

G06F 7/04

726 29

The present invention provides for a security system for an electronic device that, in one embodiment, includes a processor with a software access key encrypted thereon and a software application with a processor access key encoded therein so that operation of the electronic device and execution of the software application requires both the software access key and the processor access key.

20040064684, Apr 1, 2004

Sep 30, 2002

10/262414

Seshagiri Kalluri - Richardson TX, US
Shannon Wichman - McKinney TX, US
Ramon Trombetta - Garland TX, US

G06F009/00

712/226000

A processor is disclosed including an instruction unit and an execution unit. The instruction unit fetches and decodes a conditional execution instruction and one or more target instructions. The conditional execution instruction specifies the target instructions, a register, and a register condition, and includes pointer update information. The execution unit saves a result of each of the target instructions dependent upon the existence of the specified register condition during execution of the conditional execution instruction. When a target instruction is an instruction involving a pointer subject to update, the execution unit updates the pointer dependent upon the pointer update information. A system (e.g., a computer system) is described including the processor coupled to a memory system. A method is disclosed for conditionally executing at least one instruction, including inputting the conditional execution instruction and the target instructions.

60527463, Apr 18, 2000

Apr 14, 1998

9/059818

Seshagiri Prasad Kalluri - Austin TX
Rene M. Delgado - Austin TX
James B. Eifert - Austin TX

Motorola, Inc. - Schaumburg IL

G06F 1300

710 38

Method and apparatus for selectively enabling a pull device coupled to a multiplexed terminal connector based on the function of the terminal connector. When the terminal functions as a general purpose input/output (GPIO), the pull device is enabled on reset or on setting a control bit. For operation as a data port, the pull device is disabled, and on reset the pull device is enabled only after any pending data transaction has completed. Upon completion of the reset period the pull device is again disabled for data port operation. In one embodiment, a terminal has a first interruptible function and a second uninterruptible function. The terminal is coupled to a pull device and control logic. If the second function is active, the control logic enables the pull device with a time delay sufficient that the second function is completed prior to the enabling of the pull device.

60819154, Jun 27, 2000

Mar 30, 1998

9/050157

Seshagiri Prasad Kalluri - Austin TX
Rene Martin Delgado - Austin TX

Motorola, Inc. - Schaumbur IL

G01R 3128

714724

Method and apparatus for reducing the time required to test an integrated circuit (10) using slew rate control. Using a very slow slew rate during normal operation may reduce electromagnetic interference, while using a faster slew rate during testing may reduce the test costs. In one embodiment, terminal control circuitry (40) includes a fast test control bit (50) to select a slow slew rate during normal operation, to select a faster slew rate during functional testing, and to optionally select a variety of slew rates during a special test to more fully characterize the behavior of integrated circuit (10). In one embodiment, each pre-driver circuit (80, 81) includes a low resistance device (61, 63) which may be selectively enabled or disabled to join with capacitors (66, 67) in output driver (82) to affect the slew rate of the signal driven as an output by integrated circuit terminal (83).