Mondira Deb Pant

8368385, Feb 5, 2013

Sep 25, 2009

12/566956

Aaron M. Barton - Erie CO, US
James S. Ignowski - Fort Collins CO, US
Pablo Lopez - Fort Collins CO, US
Mondira Pant - Westborough MA, US
Rex Petersen - Fort Collins CO, US
Robert Rose - Hudson MA, US
Sean Welch - Bellingham MA, US

Intel Corporation - Santa Clara CA

G01R 19/14
G01R 31/3187

324133, 3247503

Methods and systems to detect droop events on-chip, which may include a sensor circuit located adjacent to a voltage node to convert a corresponding voltage to a digital count or value indicative of the voltage. The sensor circuit may include an n-stage ring oscillator and an asynchronous counter. The sensor circuit may include circuitry to capture and convert a phase associated with a count to a binary fractional value to increase voltage resolution. Multiple counts associated with the node may be evaluated at the node to identify minimum and maximum counts and corresponding time stamps. More complex evaluation and control circuitry may be shared amongst a plurality of sensor circuits and may include circuitry to generate and compare counts to one or more variable thresholds, circuitry to average counts over time, and memory to store state values associated with the sensors.

20070035331, Feb 15, 2007

Aug 11, 2005

11/201559

Mondira Pant - Westborough MA, US
Paul Gronowski - Northborough MA, US
Randy Allmon - North Grafton MA, US
Manjunath Bhat - Sunnyvale CA, US
David Lin - Westborough MA, US

H03K 19/096

326095000

A circuit for converting received domino logic signals to a static output signal includes a pair of logic gates having inputs and outputs that are cross-coupled and responsive to a domino logic input signal and a clock signal to latch the input signal during an evaluation phase defined by the clock signal. A static output is based on the latched value. One of the logic gates is tri-stateable to establish a value at the static output during a scan mode. A circuit for converting received static logic signals into domino logic signals includes a latch responsive to a clock signal to latch the value of a data signal at a predefined clock transition. A conversion circuit produces a domino logic output signal in response to the clock signal and the latched value of the data signal. A latch component is tri-stateable to establish a value at the output.

20070250755, Oct 25, 2007

Mar 29, 2006

11/393178

Wayne Burleson - Shutesbury MA, US
Mondira Pant - Westborough MA, US
Shubhendu Mukherjee - Framingham MA, US

G11C 29/00

714763000

In accordance with some embodiments, an error checking scheme to check for an error in a memory unit during a dormant state is provided herein.

20090085552, Apr 2, 2009

Sep 29, 2007

11/864914

Olivier Franza - Boston MA, US
Mondira Pant - Westborough MA, US
Stefan Rusu - Sunnyvale CA, US
Michael Zelikson - Haifa, IL

G06F 1/26

323350

In some embodiments of the invention, a processor with a power management scheme using dynamically switchable embedded power gates.