Kern Hyunkyoung A Rim

6603156, Aug 5, 2003

Mar 31, 2001

09/823855

Kern Rim - Peekskill NY

International Business Machines Corporation - Armonk NY

H01L 310328

257190, 257347, 257365

A SOI structure and a method for its fabrication, in which a strained silicon layer lies directly on an insulator layer, contrary to the prior requirement for strained-Si layers to lie directly on a strain-inducing (e. g. , SiGe) layer. The method generally entails the forming a silicon layer on a strain-inducing layer so as to form a multilayer structure, in which the strain-inducing layer has a different lattice constant than silicon so that the silicon layer is strained as a result of the lattice mismatch with the strain-inducing layer. The multilayer structure is then bonded to a substrate so that an insulating layer is between the strained silicon layer and the substrate, and so that the strained silicon layer directly contacts the insulating layer. The strain-inducing layer is then removed to expose a surface of the strained silicon layer and yield a strained silicon-on-insulator structure that comprises the substrate, the insulating layer on the substrate, and the strained silicon layer on the insulating layer. As a result, the method yields a strained silicon-on-insulator (SSOI) structure in which the strain in the silicon layer is maintained by the SOI structure.

6667528, Dec 23, 2003

Jan 3, 2002

10/033902

Guy Moshe Cohen - Mohegan Lake NY
Kern Rim - Yorktown Heights NY
Dennis L. Rogers - Croton-on-Hudson NY
Jeremy Daniel Schaub - Yonkers NY
Min Yang - Kingston NY

International Business Machines Corporation - Armonk NY

H01L 31058

257469, 257347, 257432, 257436, 257446, 257447, 257448, 257458, 257459, 257460, 257461, 257462, 257463, 257464, 257465, 438 48, 438 87, 438309

A photodetector (and method for producing the same) includes a semiconductor substrate, a buried insulator formed on the substrate, a buried mirror formed on the buried insulator, a semiconductor-on-insulator (SOI) layer formed on the conductor, alternating n-type and p-type doped fingers formed in the semiconductor-on-insulator layer, and a backside contact to one of the p-type doped fingers and the n-type doped fingers.

6815738, Nov 9, 2004

Feb 28, 2003

10/377388

Kern Rim - Yorktown Heights NY

International Business Machines Corporation - Armonk NY

H01L 2980

257256, 257 66, 257213, 257262, 257347, 257350

A method is disclosed for fabricating multifaceted, tensilely strained Si MOSFET (FinFET) devices. The method comprises the growing by selective epitaxy of a monocrystalline Si strip onto a monocrystalline SiGe layer sidewall surface, where the SiGe layer is bonded to a support platform, typically an insulator on a Si substrate, and where the Si strip also bonds to the support platform. The SiGe sidewall surface has a lattice constant which is larger than the relaxed lattice constant of Si, whereby the Si strip is in a tensilely strained state. Upon removing the SiGe monocrystalline layer the monocrystalline strained Si strip is turned into a multifaceted Si strip on the support platform, suitable for fabricating multifaceted gate FinFETs. Fabrication of processors with such FinFet devices is also disclosed.

7002209, Feb 21, 2006

May 21, 2004

10/851830

Xiangdong Chen - Poughquag NY, US
Dureseti Chidambarrao - Weston CT, US
Oleg Gluschenkov - Poughkeepsie NY, US
Brian Greene - Danbury CT, US
Kern Rim - Yorktown Heights NY, US
Haining S. Yang - Wappingers Falls NY, US

International Business Machines Corporation - Armonk NY

H01L 29/76
H01L 29/94
H01L 31/062
H01L 31/113
H01L 31/119

257336, 257365, 438197

The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the silicide contact, the exposed surface of the substrate adjacent to the gate region and the at least one gate region, wherein the stress inducing liner provides a stress to a device channel portion of the substrate underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 200 MPa to about 2000 MPa. The present invention also provides a method for forming the above-described semiconducting device.

7034362, Apr 25, 2006

Oct 17, 2003

10/688692

Kern Rim - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY

H01L 27/12

257351, 257347, 257623, 257627

A SOI MOSFET structure having a reduced step height between the various semiconductor layers without adversely affecting the junction capacitance of the semiconductor device formed on the uppermost semiconductor layer as well as a method of fabricating the same are provided. The structure of the present invention includes an elevated device region having at least one semiconductor device located on a second semiconductor layer. The elevated device region further includes a source/drain junction that extends from the second semiconductor layer down to a first buried insulator layer that is located on an upper surface of the semiconductor substrate. The structure also includes a recessed device region having at least one semiconductor device located atop a first semiconductor layer which is located on an upper surface of the first buried insulator. An isolation region separates the elevated device region from the recessed device region.

7129548, Oct 31, 2006

Aug 11, 2004

10/916201

Kevin K. Chan - Staten Island NY, US
Christian Lavoie - Ossining NY, US
Kern Rim - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY

H01L 29/94

257382, 257384, 257336, 257344, 257342, 257E21439, 257E29156

A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide.

7132322, Nov 7, 2006

May 11, 2005

10/908411

Brian Joseph Greene - Yorktown Heights NY, US
Kern Rim - Yorktown Heights NY, US
Clement Wann - Carmel NY, US

International Business Machines Corporation - Armonk NY

H01L 21/8238
H01L 21/8242
H01L 21/336

438199, 438242, 438258, 257E51005, 257E29137

Form a dielectric layer on a semiconductor substrate. Deposit an amorphous Si film or a poly-Si film on the dielectric layer. Then deposit a SiGe amorphous-Ge or polysilicon-Ge thin film theteover. Pattern and etch the SiGe film using a selective etch leaving the SiGe thin film intact in a PFET region and removing the SiGe film exposing the top surface of the Si film in an NFET region. Anneal to drive Ge into the Si film in the PFET region. Deposit a gate electrode layer covering the SiGe film in the PFET region and cover the exposed portion of the Si film in the NFET region. Pattern and etch the gate electrode layer to form gates. Form FET devices with sidewall spacers and source regions and drains regions in the substrate aligned with the gates.

7183175, Feb 27, 2007

Jul 1, 2005

11/172707

Steven John Koester - Ossining NY, US
Klaus Dietrich Beyer - Poughkeepsie NY, US
Michael John Hargrove - Clinton Corners NY, US
Kern Rim - Yorktown Heights NY, US
Kevin Kok Chan - Staten Island NY, US

International Business Machines Corporation - Armonk NY

H01L 21/762

438429, 438435, 257E21546

A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.