Search

Junji Sugisawa

from San Jose, CA
Age ~61
Get Report
Connected to:
Eri Sugita, 57Mayuri Sugita, 59Satoshi Sugita, 42Sharon E Sugita, 73Mutsumi Sugitani, 46Hirotaka Sugiura, 67Naoya Sugiura, 54Soichi Sugiura, 65Daisy O Sugiyama, 44Eric H Sugiyama, 43

Junji Sugisawa Phones & Addresses

  • San Jose, CA
  • 1220 Pierce St, Santa Clara, CA 95050
  • Sunnyvale, CA
  • Fort Collins, CO

Work

Position: Clerical/White Collar

Resumes

Resumes

Junji Sugisawa Photo 1

Asic Design Engineer

View page
Location:
Santa Clara, CA
Industry:
Semiconductors
Work:
Apple
Asic Design Engineer
Pa Semi
Design Engineer
Skills:
Verilog
Asic
Vlsi
Rtl Design
Ic
Soc
Debugging
Physical Design
Embedded Systems
Hardware Architecture
Fpga
Systemverilog
Very Large Scale Integration
System on A Chip
Application Specific Integrated Circuits
Junji Sugisawa Photo 2

Design Engineer

View page
Location:
Santa Clara, CA
Industry:
Semiconductors
Work:
Pa Semi
Design Engineer

Publications

Us Patents

Scannable Latch For A Dynamic Circuit

View page
US Patent:
6570407, May 27, 2003
Filed:
Jan 30, 2002
Appl. No.:
10/060456
Inventors:
Junji Sugisawa - Santa Clara CA
Larry Kan - Fremont CA
David Greenhill - Portola Valley CA
Joseph Siegel - Shrewsbury MA
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
H03K 19096
US Classification:
326 93, 326 16, 326 95, 326 98, 714724
Abstract:
A scannable latch for use within a circuit path of a series of one or more dynamic circuits is provided. The scannable latch provides both latch functionality during normal operation and scan test functionality during scan mode operation. Particularly, the scannable latch has a dynamic input stage and a shadow latch, where the dynamic input stages primary function occurs during normal operations and where the shadow latchs primary function occurs during scan operations. The scannable latch also has an output gate operatively connected to the dynamic input stage and shadow latch.

Floating Point Status/Control Register Encodings For Speculative Register Field

View page
US Patent:
7996662, Aug 9, 2011
Filed:
Nov 17, 2005
Appl. No.:
11/281832
Inventors:
Wei-Han Lien - San Jose CA, US
Daniel C. Murray - Morgan Hill CA, US
Junji Sugisawa - Santa Clara CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G06F 7/38
G06F 9/00
G06F 9/44
G06F 15/00
US Classification:
712244
Abstract:
In one embodiment, a processor comprises a plurality of storage locations, a decode circuit, and a status/control register (SCR). Each storage location is addressable as a speculative register and is configured to store result data generated during execution of an instruction operation and a value representing an update for the SCR. The value includes at least a first encoding that represents an update to a plurality of bits in the SCR, and a first number of bits in the plurality of bits is greater than a second number of bits in the first encoding. The decode circuit is coupled to receive the first encoding from a first storage location responsive to retirement of a first instruction operation assigned to use the first storage location as a destination, and is configured to decode the first encoding and generate the plurality of bits. The decode circuit is configured to update the SCR.

Shared Integer, Floating Point, Polynomial, And Vector Multiplier

View page
US Patent:
20130138711, May 30, 2013
Filed:
Nov 29, 2011
Appl. No.:
13/306460
Inventors:
Junji Sugisawa - Santa Clara CA, US
International Classification:
G06F 7/487
G06F 7/523
US Classification:
708503, 708625
Abstract:
A multiplier for performing multiple types of multiplication including integer, floating point, vector, and polynomial multiplication. The multiplier includes a modified booth encoder within the multiplier and unified circuitry to perform the various types of multiplication. A carry save adder tree is modified to route sum outputs to one part of the tree and to route carry outputs to another part of the tree. The carry save adder tree is also organized into multiple carry save adder trees to perform vector multiplication.

Boosted Differential Latch

View page
US Patent:
58252258, Oct 20, 1998
Filed:
Feb 9, 1996
Appl. No.:
8/599029
Inventors:
Junji Sugisawa - Santa Clara CA
Jean Claude Cornet - Marina Del Rey CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 3356
US Classification:
327208
Abstract:
A data latch circuit which drives an output node to a certain value without waiting for a transition at the internal latching device. The advantage is low power consumption and high performance characteristics. The difference between a conventional differential latch and a boosted differential latch is the existence of a boosting transistor device, which allows the low power advantages of the differential latch, while improving the performance.

Dynamic Scan Circuit And Method For Using The Same

View page
US Patent:
56195117, Apr 8, 1997
Filed:
Jul 30, 1996
Appl. No.:
8/692864
Inventors:
Junji Sugisawa - Santa Clara CA
Dilip Lalwani - Sunnyvale CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1100
US Classification:
371 223
Abstract:
The present disclosure describes a scan latch which utilizes dynamic interface nodes to facilitate full scan operation with a reduced number of transistors. A scan latch slave stage is coupled to a storage node of a storage device to capture data from that device. The scan latch slave device has an output driver with an input node coupled by a pass gate to the storage node. A scan clock line is coupled to the pass gate and to an enable input of the output driver. A slave scan clock signal received on the scan clock line enables the output driver and controls the pass gate. A master stage which may be utilized with the scan latch slave stage has a tri-state input device coupled to a serial input. The tri-state input device is controlled by a master scan clock and has an output coupled to the storage node.

Method And Apparatus For Low Power Data Transmission

View page
US Patent:
58314539, Nov 3, 1998
Filed:
Dec 30, 1996
Appl. No.:
8/777547
Inventors:
Georgios I. Stamoulis - Campbell CA
Junji Sugisawa - Santa Clara CA
Michael Y. Zhang - Palo Alto CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 190948
H03K 19096
US Classification:
326113
Abstract:
A method and apparatus for low power transmission of digital data. A low power data transmission circuit includes a pass gate having parallel-connected n and p-channel CMOS transistors that transmit input data. To reduce power in a first embodiment, a circuit disables the parallel-connected p-channel pass gate transistor except when the input data is high (logical 1). The p-channel pass gate transistor is needed to pass logical 1's without degradation. In the first embodiment, the n-channel pass gate transistor is enabled to transmit the input data on every clock cycle. In a second embodiment, the circuit disables the parallel-connected n-channel pass gate transistor except when the input data is low (logical 0). The n-channel pass gate transistor is needed to pass logical 0's without degradation. In this embodiment, the p-channel pass gate transistor is enabled to transmit the input data on every clock cycle.

Differential Current Switch Logic Gate

View page
US Patent:
60140410, Jan 11, 2000
Filed:
Sep 26, 1997
Appl. No.:
8/937832
Inventors:
Dinesh Somasekhar - Bangalore, IN
Kaushik Roy - West Lafayette IN
Junji Sugisawa - Fort Collins CO
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 19094
H03K 1920
US Classification:
326115
Abstract:
A differential current switch logic (DCSL) system is provided which has an evaluation tree including a plurality of input terminals and a pair of complementary output nodes. The DCSL system also has an output network which establishes a pair of state outputs at a predetermined level during a precharge phase and establishes the state outputs at complementary levels in response to the evaluation tree output nodes during an evaluate phase. First and second NMOS transistors are connected in series between the DCVS output state network and the evaluation tree output nodes with their gates coupled to the state outputs to isolate the outputs from the evaluation tree following evaluation.

Configurable Convolution Engine

View page
US Patent:
20200184000, Jun 11, 2020
Filed:
Feb 14, 2020
Appl. No.:
16/791926
Inventors:
- Cupertino CA, US
Junji Sugisawa - Santa Clara CA, US
Muge Wang - San Jose CA, US
International Classification:
G06F 17/15
G06T 5/20
G06T 5/00
G06T 1/20
Abstract:
Embodiments of the present disclosure relate to a configurable convolution engine that receives configuration information to perform convolution or its variant operations on streaming input data of various formats. To process streaming input data, input data of multiple channels are received and stored in an input buffer circuit in an interleaved manner. Data values of the interleaved input data are retrieved and forwarded to multiplier circuits where multiplication with a corresponding filter element of a kernel is performed. Varying number of kernels with different sizes and sparsity can also be used for the convolution operations.
Control profile
Junji Sugisawa from San Jose, CA, age ~61 Get Report