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Soichi Sugiura

from Bristow, VA
Age ~65

Soichi Sugiura Phones & Addresses

  • 10077 Tummel Falls Dr, Bristow, VA 20136 (703) 368-3569
  • 9323 Amaryllis Ave, Manassas, VA 20110
  • Wappingers Falls, NY
  • San Jose, CA
  • Fishkill, NY
  • 10077 Tummel Falls Dr, Bristow, VA 20136

Work

Position: Service Occupations

Education

Degree: Graduate or professional degree

Publications

Us Patents

Methods Of Forming Semiconductor Device Structures, And Related Semiconductor Device Structures

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US Patent:
20140054755, Feb 27, 2014
Filed:
Aug 21, 2012
Appl. No.:
13/590928
Inventors:
Xinyu Zhang - Bristow VA, US
Soichi Sugiura - Bristow VA, US
Yu Zeng - Woodbridge VA, US
Assignee:
MICRON TECHNOLOGY, INC. - Boise ID
International Classification:
H01L 21/31
H01L 21/3065
H01L 29/02
US Classification:
257635, 438761, 438710, 257629, 257E29002, 257E2124, 257E21218
Abstract:
A method of forming a semiconductor device structure comprises forming at least one reflective structure comprising at least two dielectric materials having different refractive indices over at least one radiation-sensitive structure, the at least one reflective structure configured to substantially reflect therefrom radiation within a predetermined wavelength range and to substantially transmit therethrough radiation within a different predetermined wavelength range. Additional methods of forming a semiconductor device structure are described. Semiconductor device structures are also described.

Memory Device Including Calibration Operation And Transistor Having Adjustable Threshold Voltage

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US Patent:
20220310620, Sep 29, 2022
Filed:
Mar 29, 2021
Appl. No.:
17/215904
Inventors:
- Boise ID, US
Jaydip Guha - Boise ID, US
Srinivas Pulugurtha - Boise ID, US
Soichi Sugiura - Bristow VA, US
International Classification:
H01L 27/108
G11C 11/4096
H01L 29/786
G11C 29/54
Abstract:
Some embodiments include apparatuses and methods using the apparatuses. One of the embodiments includes a capacitor, a transistor coupled to the capacitor, the transistor and the capacitor included in a memory cell; the transistor including a channel structure, a gate including a portion located on a side of the channel structure, and a dielectric structure between the channel structure and the gate; and on-die circuitry configured to selectively apply a stress condition to the transistor to tune a threshold voltage of the transistor.

Recessed Access Devices And Methods Of Forming A Recessed Access Devices

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US Patent:
20230062092, Mar 2, 2023
Filed:
Aug 30, 2021
Appl. No.:
17/460984
Inventors:
- Boise ID, US
Sau Ha Cheung - Boise ID, US
Richard Beeler - Boise ID, US
Ping Chieh Chiang - Boise ID, US
Hyoung Lee - Boise ID, US
Jaydip Guha - Boise ID, US
Soichi Sugiura - Bristow VA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 27/108
H01L 29/51
Abstract:
A recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator extends along sidewalls and around a bottom of the conductive gate between the conductive gate and the semiconductor material. A pair of source/drain regions are in upper portions of the semiconductor material on opposing lateral sides of the trench. A channel region in the semiconductor material below the pair of source/drain regions extends along sidewalls and around a bottom of the trench. The gate insulator comprises a low-k material and a high-k material. The low-k material is characterized by its dielectric constant k being no greater than 4.0. The high-k material is both (a) and (b), where:

Recessed Access Devices And Methods Of Forming A Recessed Access Devices

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US Patent:
20230063549, Mar 2, 2023
Filed:
Aug 25, 2021
Appl. No.:
17/411643
Inventors:
- Boise ID, US
Soichi Sugiura - Bristow VA, US
Jaydip Guha - Boise ID, US
Anthony Kanago - Boise ID, US
Richard Beeler - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 29/423
H01L 27/108
H01L 29/51
H01L 29/40
Abstract:
A method of forming a recessed access device comprises forming a trench in semiconductor material. Sidewalls and a bottom of the trench are lined with low-k gate-insulator material. The low-k gate-insulator material is characterized by its dielectric constant k being no greater than 4.0. Sacrificial material is formed in a bottom portion of the trench over the low-k gate-insulator material and over the trench bottom. A high-k gate-insulator material is formed in an upper portion of the trench above the sacrificial material and laterally-inward of the low-k gate-insulator material that is in the upper portion of the trench. The high-k gate-insulator material is characterized by its dielectric constant k being greater than 4.0. The sacrificial material is replaced with a conductive gate that has its top above a bottom of the high-k gate-insulator material. A pair of source/drain regions is formed in upper portions of the semiconductor material on opposing lateral sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions and extends along the trench sidewalls and around the trench bottom. Other embodiments, including structure independent of method, are disclosed.

Methods Of Forming Electronic Apparatus With Titanium Nitride Conductive Structures, And Related Electronic Apparatus And Systems

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US Patent:
20210358919, Nov 18, 2021
Filed:
May 14, 2020
Appl. No.:
16/874260
Inventors:
- Boise ID, US
Sanket S. Kelkar - Boise ID, US
Christopher W. Petz - Boise ID, US
Anthony J. Kanago - Boise ID, US
Brenda D. Kraus - Boise ID, US
Soichi Sugiura - Bristow VA, US
International Classification:
H01L 27/108
H01L 29/49
H01L 21/28
C23C 16/34
C23C 16/455
C23C 16/56
C23C 16/24
Abstract:
Methods for forming microelectronic devices include forming a titanium nitride (TiN) material over a precursor structure. Forming the TiN material comprises repeating cycles of flowing a titanium-including gas adjacent the precursor structure; flowing a reducing gas over the precursor structure; flowing a nitrogen-including gas over the precursor structure; and, before and after flowing the nitrogen-including gas, purging gas. Related microelectronic device and related electronic systems are also described.

Semiconductor Devices Including Transistors Comprising A Charge Trapping Material, And Related Systems And Methods

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US Patent:
20200066726, Feb 27, 2020
Filed:
Aug 21, 2018
Appl. No.:
16/107324
Inventors:
- Boise ID, US
Haitao Liu - Boise ID, US
Soichi Sugiura - Bristow VA, US
Oscar O. Enomoto - Manassas VA, US
Mark A. Zaleski - Boise ID, US
Keisuke Hirofuji - Higashihiroshima, Hiroshima,, JP
Makoto Morino - Tachikawa, Tokyo, JP
Ichiro Abe - Sagamihara, Kanagawa, JP
Yoshiyuki Nanjo - Nishiwaki, Hyogo, JP
Atsuko Otsuka - Higashihiroshima, Hiroshima, JP
International Classification:
H01L 27/108
H01L 29/423
H01L 29/66
Abstract:
A semiconductor device comprises a memory storage component and a transistor in operable communication with the memory storage element. The transistor comprises a source region, a drain region, a gate electrode between the source region and the drain region, a charge trapping material surrounding at least an upper portion of the gate electrode, and an oxide material on sides of the charge trapping material. Related systems and methods are also disclosed.

Semiconductor Device Structures Inlcuding A Distributed Bragg Reflector

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US Patent:
20160035681, Feb 4, 2016
Filed:
Oct 9, 2015
Appl. No.:
14/879363
Inventors:
- Boise ID, US
Soichi Sugiura - Bristow VA, US
Yu Zeng - Clarksville MD, US
International Classification:
H01L 23/552
H01L 23/532
Abstract:
A method of forming a semiconductor device structure comprises forming at least one reflective structure comprising at least two dielectric materials having different refractive indices over at least one radiation-sensitive structure, the at least one reflective structure configured to substantially reflect therefrom radiation within a predetermined wavelength range and to substantially transmit therethrough radiation within a different predetermined wavelength range. Additional methods of forming a semiconductor device structure are described. Semiconductor device structures are also described.
Soichi Sugiura from Bristow, VA, age ~65 Get Report