US Patent:
20200066726, Feb 27, 2020
Inventors:
- Boise ID, US
Haitao Liu - Boise ID, US
Soichi Sugiura - Bristow VA, US
Oscar O. Enomoto - Manassas VA, US
Mark A. Zaleski - Boise ID, US
Keisuke Hirofuji - Higashihiroshima, Hiroshima,, JP
Makoto Morino - Tachikawa, Tokyo, JP
Ichiro Abe - Sagamihara, Kanagawa, JP
Yoshiyuki Nanjo - Nishiwaki, Hyogo, JP
Atsuko Otsuka - Higashihiroshima, Hiroshima, JP
International Classification:
H01L 27/108
H01L 29/423
H01L 29/66
Abstract:
A semiconductor device comprises a memory storage component and a transistor in operable communication with the memory storage element. The transistor comprises a source region, a drain region, a gate electrode between the source region and the drain region, a charge trapping material surrounding at least an upper portion of the gate electrode, and an oxide material on sides of the charge trapping material. Related systems and methods are also disclosed.