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John Zoutendyk Phones & Addresses

  • 7500 E Mccormick Pkwy #34, Scottsdale, AZ 85258 (480) 609-4399
  • 7500 Mccormick Pkwy, Scottsdale, AZ 85258 (480) 609-4399
  • Artesia, NM
  • Glendale, CA

Work

Position: Retired

Education

Degree: Graduate or professional degree

Publications

Us Patents

Method Of Measuring Field Funneling And Range Straggling In Semiconductor Charge-Collecting Junctions

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US Patent:
46756019, Jun 23, 1987
Filed:
Nov 27, 1985
Appl. No.:
6/802769
Inventors:
John A. Zoutendyk - La Crescenta CA
Carl J. Malone - Los Angeles CA
Assignee:
The United States of America as represented by the Administrator of the
National Aeronautics and Space Administration - Washington DC
International Classification:
G01R 3126
US Classification:
324158R
Abstract:
Electric-field funneling length is measured while irradiating a semiconductor charge-collecting junction with electron-hole-pair generating charged particles at a first junction bias voltage. The bias voltage is then reduced to a second level in order to reduce the depth of the depletion region such that the total charge can no longer be collected by drift and measured in the energy band previously displayed in the multichannel analyzer. This is representative of the maximum electric field funnelling length which may be calculated by measuring the difference at the second bias voltage level of the depletion width and the ion penetration range. The bias voltage is further lowered to a third level at which the particles are collected over a spread of energy levels while at least some of the particles are still collected at the selected energy level. From this the different depths of penetration of the particles are determined while additional effects due to diffusion are minimized.

Method And Apparatus For Increasing Resistance Of Bipolar Buried Layer Integrated Circuit Devices To Single-Event Upsets

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US Patent:
50721330, Dec 10, 1991
Filed:
Feb 20, 1991
Appl. No.:
7/692801
Inventors:
John A. Zoutendyk - La Crescenta CA
Assignee:
The United States of America as represented by the Administrator of the
National Aeronautics and Space Administration - Washington DC
International Classification:
H03K 301
H03K 326
H03K 3284
G01T 124
US Classification:
3072962
Abstract:
Bipolar transistors fabricated in separate buried layers of an integrated circuit chip are electrically isolated with a built-in potential barrier established by doping the buried layer with a polarity opposite doping in the chip substrate. To increase the resistance of the bipolar transistors to single-event upsets due to ionized particle radiation, the substrate is biased relative to the buried layer with an external bias voltage selected to offset the built-in potential just enough (typically between about +0. 1 to +0. 2 volt) to prevent an accumulation of charge in the buried-layer-substrate junction.
John A Zoutendyk from Scottsdale, AZ, age ~88 Get Report