Inventors:
John A. Zoutendyk - La Crescenta CA
Assignee:
The United States of America as represented by the Administrator of the
National Aeronautics and Space Administration - Washington DC
International Classification:
H03K 301
H03K 326
H03K 3284
G01T 124
Abstract:
Bipolar transistors fabricated in separate buried layers of an integrated circuit chip are electrically isolated with a built-in potential barrier established by doping the buried layer with a polarity opposite doping in the chip substrate. To increase the resistance of the bipolar transistors to single-event upsets due to ionized particle radiation, the substrate is biased relative to the buried layer with an external bias voltage selected to offset the built-in potential just enough (typically between about +0. 1 to +0. 2 volt) to prevent an accumulation of charge in the buried-layer-substrate junction.