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James R Ondrusek

from Seagoville, TX
Deceased
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Also known as:
James Robert Ondrusek, Bob J Ondrusek, James R Ondrvsek, Bob K
Phone and address:
1045 Eubanks Rd, Seagoville, TX 75159
(972) 476-8857
Related to:
Lloyd F Farber, 86Crystal L Farber, 60Nancy R Ondruse, 70Amanda CopelandLoren Case, 64
Connected to:
Brian J Ondrusek, 58Hana Ondrusek, 57James R Ondrusek, 66Joseph T Ondrusek, 46Gretchen Ondrusko, 86John A Ondrush, 77Kenneth K Onduso, 43Michael S Ondy, 41James S One, 62John L One, 56

James Ondrusek Phones & Addresses

  • 1045 Eubanks Rd, Seagoville, TX 75159 (972) 476-8857 (972) 476-8869
  • Combine, TX
  • 2807 11Th St, Dallas, TX 75203
  • 1045 Eubanks Rd, Seagoville, TX 75159 (214) 226-1325

Work

Position: Food Preparation and Serving Related Occupations

Education

Degree: High school graduate or higher

Resumes

Resumes

James Ondrusek Photo 1

Director Analog And Cmos Reliability Development

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Location:
Dallas, TX
Industry:
Semiconductors
Work:
Texas Instruments
Director Analog and Cmos Reliability Development
Texas Instruments Feb 2001 - Apr 2015
Director Cmos Development Reliability
Micron Inc Sep 1998 - Jan 2001
Offshore Dram Quality Manager
Texas Instruments Jan 1994 - Sep 1998
Dram Operational Quality Manager
Skills:
Semiconductors
Ic
Semiconductor Industry
Cmos
Soc
Mixed Signal
Asic
Power Management
Analog
Spc
Design of Experiments
Electronics
Failure Analysis
Silicon
Reliability Engineering
Engineering Management
Research and Development
Reliability
Statistical Process Control
Debugging
Semiconductor Process
Embedded Memory
James Ondrusek Photo 2

James Ondrusek

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Publications

Us Patents

Method Of Stressing Static Random Access Memories For Pass Transistor Defects

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US Patent:
20130039139, Feb 14, 2013
Filed:
Feb 10, 2012
Appl. No.:
13/370451
Inventors:
Jayesh C. Raval - Allen TX, US
Beena Pious - Carrollton TX, US
Stanton Petree Ashburn - McKinney TX, US
James Craig Ondrusek - Richardson TX, US
Assignee:
TEXAS INSTRUMENTS INCORPORATED - Dallas TX
International Classification:
G11C 29/00
US Classification:
365201
Abstract:
A method of stressing and screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing initial data states into the memory array under nominal bias conditions, an elevated bias voltage is applied to the memory array, for example to its power supply node. Under the elevated bias voltage, alternating data patterns are written into and read from the memory array for a selected duration. The elevated bias voltage is reduced, and a write screen is performed to identify defective memory cells. The dynamic stress of the repeated writes and reads accelerates early life failures, facilitating the write screen.

High Voltage Finger Layout Transistor

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US Patent:
20230061337, Mar 2, 2023
Filed:
Aug 31, 2021
Appl. No.:
17/463529
Inventors:
- Dallas TX, US
Sunglyong Kim - Allen TX, US
Seetharaman Sridhar - Richardson TX, US
Sameer Pendharkar - Allen TX, US
James Craig Ondrusek - Richardson TX, US
Srikanth Krishnan - Plano TX, US
International Classification:
H01L 29/417
H01L 23/482
H01L 27/098
Abstract:
An integrated circuit, including a source region, a drain region, a channel region between the source region and the drain region, and a gate for inducing a conductive path through the channel region. The integrated circuit also includes structure, proximate a curved length of the gate, for inhibiting current flow along a portion of the channel region.
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James R Ondrusek from Seagoville, TXDeceased Get Report