Resumes
Resumes
James Ondrusek Phones & Addresses
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101 Angela Ct, Stephenville, TX 76401 (214) 460-3469
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1134 Stonewall St, Garland, TX 75043 (972) 864-5646
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19440 Fm 548, Terrell, TX 75160 (972) 524-8819
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Kaufman, TX
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Seagoville, TX
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Irving, TX
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Waco, TX
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Dallas, TX
Publications
Us Patents
Method Of Stressing Static Random Access Memories For Pass Transistor Defects
View pageUS Patent:
20130039139, Feb 14, 2013
Filed:
Feb 10, 2012
Appl. No.:
13/370451
Inventors:
Jayesh C. Raval - Allen TX, US
Beena Pious - Carrollton TX, US
Stanton Petree Ashburn - McKinney TX, US
James Craig Ondrusek - Richardson TX, US
Beena Pious - Carrollton TX, US
Stanton Petree Ashburn - McKinney TX, US
James Craig Ondrusek - Richardson TX, US
Assignee:
TEXAS INSTRUMENTS INCORPORATED - Dallas TX
International Classification:
G11C 29/00
US Classification:
365201
Abstract:
A method of stressing and screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing initial data states into the memory array under nominal bias conditions, an elevated bias voltage is applied to the memory array, for example to its power supply node. Under the elevated bias voltage, alternating data patterns are written into and read from the memory array for a selected duration. The elevated bias voltage is reduced, and a write screen is performed to identify defective memory cells. The dynamic stress of the repeated writes and reads accelerates early life failures, facilitating the write screen.
High Voltage Finger Layout Transistor
View pageUS Patent:
20230061337, Mar 2, 2023
Filed:
Aug 31, 2021
Appl. No.:
17/463529
Inventors:
- Dallas TX, US
Sunglyong Kim - Allen TX, US
Seetharaman Sridhar - Richardson TX, US
Sameer Pendharkar - Allen TX, US
James Craig Ondrusek - Richardson TX, US
Srikanth Krishnan - Plano TX, US
Sunglyong Kim - Allen TX, US
Seetharaman Sridhar - Richardson TX, US
Sameer Pendharkar - Allen TX, US
James Craig Ondrusek - Richardson TX, US
Srikanth Krishnan - Plano TX, US
International Classification:
H01L 29/417
H01L 23/482
H01L 27/098
H01L 23/482
H01L 27/098
Abstract:
An integrated circuit, including a source region, a drain region, a channel region between the source region and the drain region, and a gate for inducing a conductive path through the channel region. The integrated circuit also includes structure, proximate a curved length of the gate, for inhibiting current flow along a portion of the channel region.