Resumes
Resumes
Jakub Golab Phones & Addresses
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2005 Willow Creek Dr, Austin, TX 78741
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9400 Muskberry Cv, Austin, TX 78717
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5217 Old Spicewood Springs Rd, Austin, TX 78731
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Richardson, TX
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Dallas, TX
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Hamtramck, MI
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Birmingham, MI
Publications
Us Patents
Sliding Window Operation
View pageUS Patent:
20170024218, Jan 26, 2017
Filed:
Jul 20, 2015
Appl. No.:
14/803728
Inventors:
- San Diego CA, US
Jakub Pawel Golab - Austin TX, US
Jakub Pawel Golab - Austin TX, US
International Classification:
G06F 9/38
G06F 9/30
G06F 15/82
G06F 9/30
G06F 15/82
Abstract:
A first register has a lane storing first input data and a second register has a lane storing second input data elements. A width of the lane of the second register is equal to a width of the lane of the first register. A single-instruction-multiple-data (SIMD) lane has a lane width equal to the width of the lane of the first register. The SIMD lane is configured to perform a sliding window operation on the first input data elements in the lane of the first register and the second input data elements in the lane of the second register. Performing the sliding window operation includes determining a result based on a first input data element stored in a first position of the first register and a second input data element stored in a second position of the second register. The second position is different from the first position.
System, Apparatus, And Method For Temporary Load Instruction
View pageUS Patent:
20160357558, Dec 8, 2016
Filed:
Jun 8, 2015
Appl. No.:
14/732784
Inventors:
- San Diego CA, US
Jakub Pawel GOLAB - Austin TX, US
Jakub Pawel GOLAB - Austin TX, US
International Classification:
G06F 9/30
G06F 1/10
G06F 1/10
Abstract:
A transient load instruction for a processor may include a transient or temporary load instruction that is executed in parallel with a plurality of input operands. The temporary load instruction loads a memory value into a temporary location for use within the instruction packet. According to some examples, a VLIW based microprocessor architecture may include a temporary cache for use in writing/reading a temporary memory value during a single VLIW packet cycle. The temporary cache is different from the normal register bank that does not allow writing and then reading the value just written during the same VLIW packet cycle.