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Henry S Sheng

from San Mateo, CA
Age ~56

Henry Sheng Phones & Addresses

  • 237 Irving St, San Mateo, CA 94402 (650) 873-4846
  • 50 Northcrest Dr, South San Francisco, CA 94080 (650) 873-4846
  • Berkeley, CA
  • Oakland, CA
  • 237 Irving St, San Mateo, CA 94402

Work

Company: Synopsys Position: Group director, r and d

Education

School / High School: University of California

Skills

Eda • Verilog • Asic • Ic • Soc • Vlsi • Debugging • Semiconductors • Static Timing Analysis • Tcl

Languages

English

Ranks

Certificate: Accelerating Change Readiness and Agility

Interests

Kids • Cooking • Investing • Traveling • Electronics • Home Improvement • Reading • Gourmet Cooking • Music • The Arts • Travel • Movies • Home Decoration

Industries

Computer Software

Public records

Vehicle Records

Henry Sheng

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Address:
237 Irving St, San Mateo, CA 94402
Phone:
(650) 873-4846
VIN:
WAU2GAFC1CN162915
Make:
AUDI
Model:
A7
Year:
2012

Resumes

Resumes

Henry Sheng Photo 1

Group Director, R And D

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Location:
237 Irving St, San Mateo, CA 94402
Industry:
Computer Software
Work:
Synopsys
Group Director, R and D
Education:
University of California
University of California, Berkeley
Bachelors, Bachelor of Science, Electrical Engineering, Electrical Engineering and Computer Science, Computer Science
University of California, Berkeley
Doctorates, Doctor of Philosophy, Electrical Engineering, Electrical Engineering and Computer Science, Computer Science
Skills:
Eda
Verilog
Asic
Ic
Soc
Vlsi
Debugging
Semiconductors
Static Timing Analysis
Tcl
Interests:
Kids
Cooking
Investing
Traveling
Electronics
Home Improvement
Reading
Gourmet Cooking
Music
The Arts
Travel
Movies
Home Decoration
Languages:
English
Certifications:
Accelerating Change Readiness and Agility
Henry Sheng Photo 2

Henry Sheng San Jose, CA

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Work:
Bank of China

Sep 2012 to Dec 2012
Marketing Analyst and Consultant

Bank of China

Jul 2012 to Dec 2012
Introductory Brokerage Intern

SJ Ink
San Jose, CA
Jun 2010 to Jun 2012
Founder and Leader

Round Table Pizza
Santa Clara, CA
Jun 2011 to Sep 2011
Franchising Analyst

Insane Ink
San Jose, CA
Aug 2008 to Jun 2010
Chief Executive Officer

Education:
Santa Clara University
Santa Clara, CA
Mar 2014
B.S. in Finance

Fudan University
Sep 2013 to Dec 2013
research

Henry Sheng Photo 3

Henry Sheng San Jose, CA

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Work:
Bank of China

Jul 2012 to Sep 2013
Introductory Brokerage Intern

Norvisdom

Sep 2012 to Dec 2012
Marketing Analyst and Consultant

SJ Ink
San Jose, CA
Jun 2010 to Jun 2012
Founder and Leader

Round Table Pizza
Santa Clara, CA
Jun 2011 to Sep 2011
Franchising Analyst

Insane Ink
San Jose, CA
Aug 2008 to Jun 2010
Chief Executive Officer

Education:
Santa Clara University
Santa Clara, CA
2010 to 2014
B.S. in Finance

Fudan University
2012
Business

Publications

Us Patents

Optimizing Logic Synthesis For Environmental Insensitivity

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US Patent:
20130263069, Oct 3, 2013
Filed:
Mar 28, 2012
Appl. No.:
13/432935
Inventors:
Chaeryung Park - Saratoga CA, US
Henry Sheng - San Mateo CA, US
Assignee:
SYNOPSYS, INC. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716104
Abstract:
Roughly described, a method for synthesizing a circuit design from a logic design includes developing candidate solutions for a particular signal path, a first candidate solution identifying a first library cells followed immediately downstream thereof by a first set of zero or more buffers, and a second candidate solution identifying a second library cell followed immediately downstream thereof by a second set of zero or more buffers, the first library cell and first set of buffers in combination being different from the second library cell and second set of buffers in combination. The computer system selects among the candidate solutions at least in part in dependence upon sensitivity of the solution to load capacitance in the particular path, and stores the selected solution in the storage for subsequent use in further developing and fabricating an integrated circuit device.

Method And Apparatus To Perform Footprint-Based Optimization Simultaneously With Other Steps

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US Patent:
20140007035, Jan 2, 2014
Filed:
Jun 28, 2012
Appl. No.:
13/536903
Inventors:
Cristian Eugen Golovanov - Allentown PA, US
Henry Shiu-Wen Sheng - San Mateo CA, US
International Classification:
G06F 17/50
US Classification:
716119, 716134
Abstract:
A method comprising placing elements in a layout, performing clock tree synthesis, and performing routing. The method further comprising, in parallel with one of the clock tree synthesis or the routing, performing a footprint based optimization, substituting a footprint equivalent element in a path based on a timing slack of the path.

Pin Accessibility Prediction Engine

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US Patent:
20200364394, Nov 19, 2020
Filed:
May 15, 2020
Appl. No.:
16/875844
Inventors:
- Mountain View CA, US
Hsien-Shih Chiu - Taipei, TW
Shao-Yun Fang - Taipei, TW
Kai-Shun Hu - Taipei, TW
Philip Hui-Yuh Tai - Cupertino CA, US
Cindy Chin-Fang Shen - Taipei, TW
Henry Sheng - Mountain View CA, US
International Classification:
G06F 30/398
G06N 3/08
G06N 3/04
G06F 16/903
Abstract:
An efficient electronic structure for circuit design, testing and/or manufacture for validating a cell layout design using an intelligent engine trained using selectively arranged cells selected from a cell library. An initial design rule violation (DRV) prediction engine is initially trained using a plurality of pin patterns generated by predefined cell placement combinations, where pin patterns are pixelized and quantified and is classified as either (i) a DRV pin pattern (i.e., pin patterns likely to produce a DRV) or (ii) a DRV-clean pin pattern (i.e., pin patterns unlikely to produce a DRV).
Henry S Sheng from San Mateo, CA, age ~56 Get Report