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Hanwoo Cho

from Las Vegas, NV
Age ~57
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Also known as:
Han W Cho, Woo Cho Han
Related to:
Lin Fang Cho, 80Fang L ChoShanshan S Li, 44Lichao Wang, 59Chinkuei Fullbright, 70
Connected to:
Abraham Cho, 47Aesop Cho, 67Ah M Cho, 77Alan Cho, 44Albert W Cho, 58Ali S Cho, 34Andre T Cho, 44Angie E Cho, 43Anna Cho, 60Annabel K Cho, 39

Hanwoo Cho Phones & Addresses

  • Las Vegas, NV
  • San Diego, CA
  • Cupertino, CA
  • 1786 Wedgewood Cmn, Concord, MA 01742
  • 38 Faulkner Hill Rd, Acton, MA 01720 (978) 929-9296
  • Malden, MA
  • 38 Faulkner Hill Rd, Acton, MA 01720

Publications

Us Patents

Dynamic Initialization Of Processor Module Via Motherboard Interface

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US Patent:
6772328, Aug 3, 2004
Filed:
Jun 18, 1999
Appl. No.:
09/335939
Inventors:
Gerald Talbot - Concord MA
Hanwoo Cho - Concord MA
Eric Rowe - Natick MA
Assignee:
Samsung Electronics Co., Ltd.
International Classification:
G06F 15177
US Classification:
713 1, 713 2, 710 8
Abstract:
In a common processor module/motherboard interface, an interface protocol is defined such that a replacement processor module can be recognized by a common motherboard and such that a common processor module can be compatible with multiple motherboards. A module information field stored on a processor module includes status information pertaining to the processor module. When the processor module is coupled to a motherboard, the motherboard downloads the module information field and generates initialization commands for the processor module based on the retrieved module information field. The commands are transferred to the processor module for initialization of the processor.

Microprocessor Module With Integrated Voltage Regulators

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US Patent:
6865682, Mar 8, 2005
Filed:
Jun 18, 1999
Appl. No.:
09/335940
Inventors:
Gerald Talbot - Concord MA, US
Hanwoo Cho - Concord MA, US
Assignee:
Samsung Electronics Co., Ltd.
International Classification:
G06F001/26
G06F013/00
G05F001/02
US Classification:
713300, 710301, 323271, 323282
Abstract:
In a microprocessor module assembly, voltage regulators are integrated into the module and adapted for use with a processor and support electronics likewise mounted on the module. The voltage regulators receive a fixed imput voltage from a motherboard interface and provide modified regulated output voltages to the processor and support electronics. In this manner, the processor module is readily upgradable such that future generations are compatible with a fixed motherboard interface without the need for upgrading voltage regulators on the motherboard. In a preferred embodiment, bulk decoupling capacitance is provided on the processor assembly to stabilize the DC output voltage of the voltage regulators.

Programmable Delay Module Testing Device And Methods Thereof

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US Patent:
8274272, Sep 25, 2012
Filed:
Feb 6, 2009
Appl. No.:
12/366973
Inventors:
Gerald R. Talbot - Concord MA, US
Hanwoo C. Cho - Acton MA, US
Brian Amick - Brookline MA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G01R 25/00
G01R 31/02
US Classification:
324 7677, 324537
Abstract:
A data processing device is configured so that, in a test mode of operation, the phase of an output signal of a second programmable delay module (PDM) is based on the phase of the input signal of the first PDM. To test the first and second PDMs, the output signal of the first PDM is set to each of a first set of phases and the corresponding phase of the output signal of the second PDM is compared to determine whether the performance of the first and second PDMs match a specification. Accordingly, the first and second PDMs are qualified based on their relative performance, reducing the need for test structures that consume an undesirably large amount of area.

Dynamic Ram Phy Interface With Configurable Power States

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US Patent:
8356155, Jan 15, 2013
Filed:
Oct 22, 2010
Appl. No.:
12/910412
Inventors:
Shawn Searles - Austin TX, US
Nicholas T. Humphries - Austin TX, US
Brian W. Amick - Bedford MA, US
Richard W. Reeves - Westborough MA, US
Hanwoo Cho - Acton MA, US
Ronald L. Pettyjohn - Concord MA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 12/00
US Classification:
711167, 711E12001
Abstract:
A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.

Memory Diagnostics System And Method With Hardware-Based Read/Write Patterns

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US Patent:
8607104, Dec 10, 2013
Filed:
Dec 20, 2010
Appl. No.:
12/972977
Inventors:
Hanwoo Cho - Acton MA, US
Tahsin Askar - Round Rock TX, US
Philip E. Madrid - Austin TX, US
Guhan Krishnan - Chelmsford MA, US
Brian W. Amick - Bedford MA, US
Shawn Searles - Austin TX, US
Ryan J. Hensley - Austin TX, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 11/00
US Classification:
714716
Abstract:
A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output.

Pci-X Error Correcting Code (Ecc) Pin Sharing Configuration

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US Patent:
7269679, Sep 11, 2007
Filed:
Jun 14, 2005
Appl. No.:
11/151317
Inventors:
Hanwoo Cho - Acton MA, US
Richard W. Reeves - Westborough MA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 13/36
US Classification:
710311, 710104, 710316, 714 1
Abstract:
A method is provided for utilizing four error correcting code (ECC) pin connections of a PCI/PCI-X bus for one of Grant (GNT) and Request (REQ) pin connections. The method determines a mode of the PCI bus to be PCI-X Mode 1, PCI-X Mode 2, or PCI. If the determined mode is PCI-X Mode 2, the four ECC pin connections are used as ECC pin connections, and if the determined mode is PCI or PCI-X Mode 1, each of the four ECC pin connections is used as a GNT pin connection or a REQ pin connection.

Automatic Processor Overclocking

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US Patent:
20090235108, Sep 17, 2009
Filed:
Mar 11, 2008
Appl. No.:
12/045916
Inventors:
Spencer M. Gold - Pepperell MA, US
Alex Branover - Brookline MA, US
Hanwoo Cho - Acton MA, US
Sebastien Nussbaum - Lexington MA, US
International Classification:
G06F 1/00
US Classification:
713500
Abstract:
Processor overclocking techniques are disclosed. Upon automatically determining that overclocking entry criteria are satisfied, one or more cores are clocked above their standard operation frequencies. The cores may be overclocked until one or more exit criteria are satisfied. At that point, an exit procedure is performed, with the one or more overclocked cores return to their normal operating frequency.

Functional Block Level Thermal Control

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US Patent:
20100073068, Mar 25, 2010
Filed:
Sep 22, 2008
Appl. No.:
12/235155
Inventors:
Hanwoo Cho - Acton MA, US
Alexander Branover - Chestnut Hill MA, US
Jonathan D. Hauke - Lexington MA, US
International Classification:
H03K 3/011
US Classification:
327513
Abstract:
An integrated circuit. The integrated circuit includes a plurality of functional units, wherein each of the plurality of functional units is implemented on a die of the integrated circuit. Each of the functional units includes one or more temperature sensors. The integrated circuit further includes a temperature control unit coupled to each of the functional units, wherein the temperature control unit is configured to monitor a temperature of each of the plurality of functional units based on temperature information provided from the temperature sensors. The temperature control unit is configured to, if the temperature exceeds a first threshold value for a particular one of the plurality of functional units, perform a first temperature control action on the particular one of the plurality of functional units independently of other ones of the plurality of functional units.
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Hanwoo Cho from Las Vegas, NV, age ~57 Get Report