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Georgi Z Beloev

from Walnut Creek, CA
Age ~52
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Also known as:
Beloev Georgi
Phone and address:
109 Roble Rd, Walnut Creek, CA 94597
(925) 944-6367
Connected to:
Alan W Beloff, 69Pamela B Beloff, 73Rosalie A Beloff, 97Harold Belofsky, 98Stuart M Belofsky, 73Olga A Belogolova, 37Christine A Belohlavek, 75Collin M Beloin, 33Leslie J Beloit, 43Brett E Belokin, 55

Georgi Beloev Phones & Addresses

  • 109 Roble Rd, Walnut Creek, CA 94597 (925) 944-6367
  • 109 Roble Rd APT 206, Walnut Creek, CA 94597 (925) 639-4314
  • Mendham, NJ
  • San Jose, CA
  • Mountain View, CA

Skills

Hardware Design • Performance Tuning • DSP • C++ • C • Embedded Systems • Microcontrollers • Blackfin • ARM • MIPS • RISC • SIMD • AVR • Microchip PIC • Microprocessors • Digital Design • Firmware • Digital Electronics • Embedded Software • Digital Signal Processors • PCB design • Computer Architecture • Digital Audio • Algorithms • Digital Video • Hardware Architecture • Software Development • Verilog • FPGA • Assembly Language • Debugging • Processors • Hardware • Digital Signal Processing • I2C • SPI

Industries

Computer Software

Resumes

Resumes

Georgi Beloev Photo 1

Sr. Iphone/Ipad Accessories Firmware Engineer At Apple

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Location:
Walnut Creek, California
Industry:
Computer Software
Skills:
Hardware Design
Performance Tuning
DSP
C++
C
Embedded Systems
Microcontrollers
Blackfin
ARM
MIPS
RISC
SIMD
AVR
Microchip PIC
Microprocessors
Digital Design
Firmware
Digital Electronics
Embedded Software
Digital Signal Processors
PCB design
Computer Architecture
Digital Audio
Algorithms
Digital Video
Hardware Architecture
Software Development
Verilog
FPGA
Assembly Language
Debugging
Processors
Hardware
Digital Signal Processing
I2C
SPI

Publications

Us Patents

Processor Having A Data Mover Engine That Associates Register Addresses With Memory Addresses

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US Patent:
20070174598, Jul 26, 2007
Filed:
Jan 23, 2006
Appl. No.:
11/336923
Inventors:
Radhika Thekkath - Palo Alto CA, US
Georgi Beloev - Walnut Creek CA, US
Assignee:
MIPS Technologies, Inc. - Mountain View CA
International Classification:
G06F 9/44
US Classification:
712234000
Abstract:
A RISC processor having a data moving engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate software accessible register addresses with memory addresses. These associations effect the operation of the data moving engine such that, for the duration of the associations, the data moving engine routes data to and from associated memory addresses and the execution unit of the processor in response to instructions that specify moving data to and from the associated register addresses. The invention reduces the number of instructions and hardware overhead associated with implementing program loops in a RISC processor.

System And Method For Improving Memory Transfer

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US Patent:
20100199054, Aug 5, 2010
Filed:
Jan 5, 2010
Appl. No.:
12/652598
Inventors:
Kevin D. Kissell - Menlo Park CA, US
Georgi Z. Beloev - Walnut Creek CA, US
Assignee:
MIPS Technologies, Inc. - Sunnyvale CA
International Classification:
G06F 12/16
US Classification:
711162, 711E12103
Abstract:
System and method for performing a high-bandwidth memory copy. Memory transfer instructions allow for copying of data from a first memory location to a second memory location without the use of load and store word instructions thereby achieving a high-bandwidth copy. In one embodiment, the method includes the steps of (1) decoding a destination address from a first memory transfer instruction, (2) storing the destination address in a register in the bus interface unit, (3) decoding a source address from a second memory transfer instruction, and (4) copying the contents of a memory location specified by the source memory address to a memory location specified by the contents of the register. Other methods and a microprocessor system are also presented.

Methods And Apparatus For Synchronization Among Integrated Circuits Within A Wireless Network

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US Patent:
20130343365, Dec 26, 2013
Filed:
Jun 7, 2013
Appl. No.:
13/913297
Inventors:
Girault Jones - Cupertino CA, US
Georgi Beloev - Walnut Creek CA, US
International Classification:
H04W 56/00
US Classification:
370338, 370350
Abstract:
Methods and apparatus for synchronization of integrated circuits (ICs) within a wireless network. In one embodiment, a serial time protocol (STP) is disclosed for use within a wireless device of a wireless network. The disclosed STP provides a common protocol for communicating precision time information from one time-transmitter IC to another time-receiver IC within a wireless device. In one exemplary implementation, a time-transmitter and a time-receiver are implemented within the firmware of a wireless device. Various schemes utilizing the disclosed STP for time synchronization are also described.

Methods And Apparatus For Equalization Of A High Speed Serial Bus

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US Patent:
20160267044, Sep 15, 2016
Filed:
Mar 6, 2015
Appl. No.:
14/641170
Inventors:
- Cupertino CA, US
Zhiping YANG - Cupertino CA, US
Kirill KALINICHEV - San Francisco CA, US
Greg NAYMAN - Mountain View CA, US
Georgi Beloev - Cupertino CA, US
International Classification:
G06F 13/42
G06F 1/32
G06F 13/40
Abstract:
Methods and apparatus for equalization of a high speed serial bus. Various aspects of the present disclosure are directed to a well-tuned passive equalization circuit for use with high frequency differential signals that suffer from e.g., impedance mismatches, impedance discontinuities (e.g., connectors, etc.). In one embodiment, a shunting circuit is inserted between the differential terminals of a Universal Serial Bus (USB) cable, connector, etc. The shunting circuit is configured to “open” at low frequencies to enable Full Speed (FS) enumeration, while also providing sufficiently high impedance at high frequencies to enable High Speed (HS) operation. In one such implementation, the shunting circuit includes a tuned resistor, capacitor, inductor, and switch element arranged in series.

System And Method For Improving Memory Transfer

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US Patent:
20160098206, Apr 7, 2016
Filed:
Nov 30, 2015
Appl. No.:
14/953862
Inventors:
- Cambridge, GB
Kevin D. Kissell - Menlo Park CA, US
Georgi Z. Beloev - Walnut Creek CA, US
International Classification:
G06F 3/06
G06F 13/16
G06F 12/08
Abstract:
System and method for performing a high-bandwidth memory copy. Memory transfer instructions allow for copying of data from a first memory location to a second memory location without the use of load and store word instructions thereby achieving a high-bandwidth copy. In one embodiment, the method includes the steps of (1) decoding a destination address from a first memory transfer instruction, (2) storing the destination address in a register in the bus interface unit, (3) decoding a source address from a second memory transfer instruction, and (4) copying the contents of a memory location specified by the source memory address to a memory location specified by the contents of the register. Other methods and a microprocessor system are also presented.
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Georgi Z Beloev from Walnut Creek, CA, age ~52 Get Report