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George Adrian Maxim

from Saratoga, CA
Age ~56

George Maxim Phones & Addresses

  • 18677 Paseo Lado, Saratoga, CA 95070 (408) 680-6991
  • San Jose, CA
  • Milpitas, CA
  • Austin, TX

Work

Company: Qorvo, inc. Jan 2015 to Aug 2019 Position: Senior principal system architect, technical lead

Education

Degree: Doctorates, Doctor of Philosophy

Skills

Mixed Signal • Analog • Simulations • Rf • Cmos • Semiconductors • Ic • Asic • Pll • Soc • Analog Circuit Design • Circuit Design • Spectre • Vco • Serdes • Lna • Bicmos • Digital Electronics • Integrated Circuit Design • Microwave • Filters • Wireless • Fpga • Pcb Design • Cadence Virtuoso • Debugging • Rf Design • Eda • Adcs • Vlsi • Electronics • Verilog • Power Management • Embedded Systems • Hardware Architecture • Cellular Communications • Oscillators • System Architecture • Customer Engagement • Team Leadership • Team Building • Team Management • Cross Functional Team Leadership

Languages

English • French

Industries

Semiconductors

Resumes

Resumes

George Maxim Photo 1

Ecole Nationale Superieure D'electronique

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Location:
18677 Paseo Lado, Saratoga, CA 95070
Industry:
Semiconductors
Work:
Qorvo, Inc. Jan 2015 - Aug 2019
Senior Principal System Architect, Technical Lead

Rfmd Nov 2012 - Jan 2015
Senior Principal System Architect, Technical Lead

Amalfi Semiconductor Apr 2010 - Nov 2012
Senior Principal System Architect, Chief Technology Officer Office

Apr 2010 - Nov 2012
Ecole Nationale Superieure D'electronique
Skills:
Mixed Signal
Analog
Simulations
Rf
Cmos
Semiconductors
Ic
Asic
Pll
Soc
Analog Circuit Design
Circuit Design
Spectre
Vco
Serdes
Lna
Bicmos
Digital Electronics
Integrated Circuit Design
Microwave
Filters
Wireless
Fpga
Pcb Design
Cadence Virtuoso
Debugging
Rf Design
Eda
Adcs
Vlsi
Electronics
Verilog
Power Management
Embedded Systems
Hardware Architecture
Cellular Communications
Oscillators
System Architecture
Customer Engagement
Team Leadership
Team Building
Team Management
Cross Functional Team Leadership
Languages:
English
French

Publications

Us Patents

Power Amplifier With Power Feedback

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US Patent:
8344806, Jan 1, 2013
Filed:
Sep 29, 2010
Appl. No.:
12/893643
Inventors:
Stephen Franck - Felton CA, US
Baker Scott - San Jose CA, US
George Maxim - Milpitas CA, US
Assignee:
Amalfi Semiconductor, Inc. - Los Gatos CA
International Classification:
H03G 3/30
US Classification:
330285, 330297
Abstract:
A power amplifier using a drain (collector) power control loop in which the feedback signal is an estimated output power level computed with a linear summation of the output sensed voltage and current. Both RF and baseband voltage and current sensing are possible, and voltage-mode or current-mode signal processing are feasible. This control loop technique is applicable to any means of drain power control circuits such as: supply regulators, DC-DC converters and others. Voltage error amplifiers can be used in conjunction with voltage feedback network, while current error amplifiers can be used with current feedback networks. Regulator sharing between different bands may be used as an area and cost reduction solution. The linear voltage and current summation driven power control technique can be also applied to the gate (base) power control scheme. Similarly, voltage-mode and current-mode signal processing can be implemented.

Power Amplifier With Back-Off Efficiency

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US Patent:
8432224, Apr 30, 2013
Filed:
Sep 29, 2010
Appl. No.:
12/893653
Inventors:
Chong Woo - Fremont CA, US
Stephen Frank - Felton CA, US
Dongmei Cao - Irvine CA, US
Baker Scott - San Jose CA, US
George A. Maxim - Milpitas CA, US
Assignee:
Amalfi Semiconductor, Inc. - Los Gatos CA
International Classification:
H03G 3/30
US Classification:
330285, 330279
Abstract:
A power amplifier system is provided with a signal path including driver stages and output stages. A power control element has one or more control ports and uses one or more nonlinear control characteristics.

Ground Partitioned Power Amplifier For Stable Operation

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US Patent:
8604873, Dec 10, 2013
Filed:
Dec 2, 2011
Appl. No.:
13/310611
Inventors:
Baker Scott - San Jose CA, US
George Maxim - Milpitas CA, US
Stephen Franck - Felton CA, US
Chu Hsiung Ho - Milpitas CA, US
Assignee:
RF Micro Devices (Cayman Islands), Ltd. - Greensboro NC
International Classification:
H03F 1/38
US Classification:
330112, 330 99, 330104
Abstract:
Achievement of robust stability of a power amplifier (PA) that allows the sharing of the ground between the driver stages and the output stage is shown. A controlled amount of negative feedback is used to neutralize the local positive feedback that results from the driver-to-output stage ground sharing in the signal path, for example, a radio frequency (RF) signal path. The solution keeps a strong drive and a good performance of the PA. Exemplary embodiments are shown for the PA positive feedback neutralization. A first embodiment uses a ground signal divider while another embodiment uses a ground signal divider weighting technique.

Output Stage Of A Power Amplifier Having A Switched-Bulk Biasing And Adaptive Biasing

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US Patent:
8624678, Jan 7, 2014
Filed:
Dec 2, 2011
Appl. No.:
13/310623
Inventors:
Baker Scott - San Jose CA, US
George Maxim - Milpitas CA, US
Stephen Franck - Felton CA, US
Assignee:
RF Micro Devices (Cayman Islands), Ltd. - Greensboro NC
International Classification:
H03F 1/22
US Classification:
330311, 330285, 330310
Abstract:
A power amplifier (PA) using switched-bulk biasing to minimize the risk of output stage snapback effect is disclosed. An adaptive biasing of the output stage prevents device breakdown while accommodating large voltage swings. These protection techniques can be applied to all types of cascode configurations of a PA, including single-ended, differential, quadrature, segmented and any combination thereto.

Power Amplifier Having A Nonlinear Output Capacitance Equalization

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US Patent:
8629725, Jan 14, 2014
Filed:
Dec 2, 2011
Appl. No.:
13/310568
Inventors:
Baker Scott - San Jose CA, US
George Maxim - Milpitas CA, US
Chu Hsiung Ho - Milpitas CA, US
Stephen Franck - Felton CA, US
Tom Biedka - San Jose CA, US
Assignee:
RF Micro Devices (Cayman Islands), Ltd. - Greensboro NC
International Classification:
H03F 3/191
US Classification:
330305, 330310
Abstract:
Power amplifier (PA), regardless of the process used for the manufacturing of its devices, suffers from a nonlinear output capacitance that has significant impact on various aspects of the PA performance. This output capacitance is dependent on the large output voltage swing. Accordingly a compensation capacitance is added at the output of the PA that has a behavior that is inverse respective of the output voltage of that of the output capacitance of the PA. Connecting the compensation capacitor in parallel to the PA output capacitance, results in a total capacitance that is the sum of the output capacitance and its compensation capacitance. The total output capacitance is therefore essentially stable throughout the output voltage swing.

Power Amplifier System With A Current Bias Signal Path

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US Patent:
20120139636, Jun 7, 2012
Filed:
Dec 2, 2011
Appl. No.:
13/310577
Inventors:
Baker Scott - San Jose CA, US
George Maxim - Milpitas CA, US
Assignee:
AMALFI SEMICONDUCTOR, INC. - Los Gatos CA
International Classification:
H03F 3/04
H03G 3/30
US Classification:
330285, 330296
Abstract:
Power amplifier (PA) systems are typically comprised of a signal path integrated circuit (IC) and a power control IC. Advanced CMOS technologies may allow smart integration of such ICs into a single IC and provide an opportunity to improve performance and cost. Specifically, the radio frequency (RF) signal path is designed to enable local biasing of the gain stages that comprise the RF signal path. By using current-mode biasing instead of the prior art voltage-mode biasing significant area reduction is achieved as well as better isolation between the stages which reduces noise, and improves stability.

Multi-Band/Multi-Mode Power Amplifier With Signal Path Hardware Sharing

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US Patent:
20140015603, Jan 16, 2014
Filed:
Jul 17, 2012
Appl. No.:
13/551473
Inventors:
Baker Scott - San Jose CA, US
George Maxim - Milpitas CA, US
Assignee:
AMALFI SEMICONDUCTOR, INC. - Los Gatos CA
International Classification:
H03F 3/20
H03F 3/68
US Classification:
330126, 330148, 330147
Abstract:
Existing multi-band/multi-mode (MB/MM) power amplifiers (PAs) use separate signal paths for the different covered frequency bands. This results in a large degree of hardware duplication and to a large die size and cost. Solutions that achieve hardware sharing between the different signal paths of MB/MM PAs are shown. Such sharing includes bias circuit and bypass capacitors sharing, as well as sharing front-end stages and the output stage of the PA. Signal multiplexing may be realized in the transmitter or at the PA front-end while the signal de-multiplexing can be realized either in the PA output stage or at the front-end of the output stage. Such circuits can be applied with saturated and linear MB/MM PAs with adjacent or non-adjacent bands.

Power Amplifier With Protection Loop

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US Patent:
20230094883, Mar 30, 2023
Filed:
Sep 29, 2021
Appl. No.:
17/488823
Inventors:
- Greensboro NC, US
Stephen James Franck - Felton CA, US
George Maxim - Saratoga CA, US
Chong Woo - Fremont CA, US
International Classification:
H03F 1/52
H03F 3/195
H03F 3/24
Abstract:
A power amplifier includes an over-current protection loop and/or an over-voltage protection loop to assist in preventing operation outside a safe operation zone. In a further exemplary aspect, triggering of the over-current protection loop adjusts a threshold voltage for the over-voltage protection loop. In further exemplary aspects, the over-current protection loop may adjust not only a bias regulator, but also provide an auxiliary control signal that further limits signals reaching the power amplifier. In still further exemplary aspects, the over-voltage protection loop may operate independently of the over-current protection current loop or the over-voltage protection loop contribute to an over-current protection signal.
George Adrian Maxim from Saratoga, CA, age ~56 Get Report