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Gary P Mcclannahan

from Marion, IA
Age ~58
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Also known as:
Gary Paul Mcclannahan, Gary Mc Clannahan, Melody Mcclannahan, Gary Mclannahan
Phone and address:
2710 Spoonbill Dr, Midway, IA 52302
Related to:
Lawrence Mroz, 76Philip Hogan, 89Herbert HarmanLinde Goza, 48Kathilou Hogan, 67Philip Hogan, 66
Connected to:
Donald L Mcclannan, 94Kristyn B Mcclannahan, 62Kurt E Mcclannan, 53Edward J Mcclaran, 58Mark R Mcclaran, 71Patricia L Mcclaran, 69Ray Mcclaran, 73Allen E Mcclard, 88Ashly Mcclard, 53Carolyn A Mcclaren, 65

Gary Mcclannahan Phones & Addresses

    s
  • 2710 Spoonbill Dr, Marion, IA 52302
  • Cedar Rapids, IA
  • 2645 Colleen St NE, Rochester, MN 55906 (507) 282-7442
  • 4015 Alberta Dr NE, Rochester, MN 55906
  • Mondamin, IA
  • 2645 Colleen St NE, Rochester, MN 55906

Resumes

Resumes

Gary Mcclannahan Photo 1

Staff Engineer

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Location:
2710 Spoonbill Dr, Marion, IA 52302
Industry:
Aviation & Aerospace
Work:
Brocade since Jan 2007
Staff ASIC Engineer
Silverback Systems Feb 2005 - Jan 2007
Member Technical Staff
LSI Logic Dec 2000 - Oct 2004
HW Engineer
IBM Jun 1988 - Dec 2000
Advisory Engineer
Education:
University of Minnesota-Twin Cities 1988 - 1995
MS, Electrical Engineering Iowa State University 1984 - 1988
BS, Computer Engineering
Skills:
Asic
Verilog
Systemverilog
Debugging
Ethernet
Fpga
Soc
Tcp/Ip
Simulations
Vhdl
Embedded Systems
Php
Specman
Rtl Design
Pcie
Processors
Networking
Encryption
Aes
Device Drivers
Gary Mcclannahan Photo 2

Gary Mcclannahan

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Publications

Us Patents

Memory Controller With Programmable Delay Counter For Tuning Performance Based On Timing Parameter Of Controlled Memory Storage Device

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US Patent:
6438670, Aug 20, 2002
Filed:
Oct 2, 1998
Appl. No.:
09/166004
Inventors:
Gary Paul McClannahan - Rochester MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1200
US Classification:
711167, 711168, 711169, 710240, 713401, 365194
Abstract:
A memory controller circuit arrangement and method utilize a tuning circuit that controls the timing of memory control operations via one or more programmable delay counters. Each counter is programmed to cycle a selected number of clock cycles to delay performance of a memory control operation to meet a predetermined timing parameter for a memory storage device coupled to the controller. Through the use of programmable delay counters, a variety of memory storage devices having varying timing parameters may be supported by the same memory controller design. Moreover, the use of programmable delay counters permit a single path of execution in a memory controller state machine to support any number of timing parameter variations for a particular timing characteristic, as well as multiple timing characteristics.

Method And Apparatus For Direct Memory Access (Dma) With Dataflow Blocking For Users

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US Patent:
6453366, Sep 17, 2002
Filed:
Feb 18, 1999
Appl. No.:
09/251043
Inventors:
Robert Neal Carlton Broberg, III - Rochester MN
Jonathan William Byrn - Kasson MN
Chad B. McBride - Rochester MN
Gary Paul McClannahan - Rochester MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1328
US Classification:
710 26, 710 28
Abstract:
A method and apparatus are provided for implementing direct memory access (DMA) with dataflow blocking for users for processing data communications in a communications system. A DMA starting address register receives an initial DMA starting address and a DMA length register receives an initial DMA length. A DMA state machine receives a control input for starting the DMA. The DMA state machine updates the DMA starting address to provide a current DMA starting address. The DMA state machine loads a DMA ending address. A DMA blocking logic receives the current DMA starting address and the DMA ending address and blocks received memory requests only within a current active DMA region.

Dynamically-Tunable Memory Controller

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US Patent:
6453434, Sep 17, 2002
Filed:
Aug 23, 2001
Appl. No.:
09/938161
Inventors:
Gary Scott Delp - Rochester MN
Gary Paul McClannahan - Rochester MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 2900
US Classification:
714718, 711167, 710240, 365194
Abstract:
A memory controller circuit arrangement and method utilize a tuning circuit that dynamically controls the timing of memory control operations, rather than simply relying on fixed timing parameters that are either hardwired or initialized upon startup of a memory controller. Dynamic control over the timing of memory control operations typically incorporates memory test control logic that verifies whether or not a memory storage device will reliably operate using the dynamically-selected values of given timing parameters. Then, based upon the results of such testing, such dynamically-selected values are selectively updated and retested until optimum values are found. The dynamically-selected values may be used to set one or more programmable registers, each of which may in turn be used to control the operation of a programmable delay counter that enables a state transition in a state machine logic circuit to initiate performance of a memory control operation by the logic circuit. Dynamic tuning may also utilize a unique binary search engine circuit arrangement that updates one of two registers with an average of the current values stored in such registers based upon the result of a test performed using that average value. By selectively updating such registers, a fast convergence to an optimum value occurs with minimal circuitry.

Communications Methods And Gigabit Ethernet Communications Adapter Providing Quality Of Service And Receiver Connection Speed Differentiation

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US Patent:
6498782, Dec 24, 2002
Filed:
Feb 3, 1999
Appl. No.:
09/243956
Inventors:
Mark William Branstad - Rochester MN
Jonathan William Byrn - Kasson MN
Gary Scott Delp - Rochester MN
Philip Lynn Leichty - Rochester MN
Todd Edwin Leonard - Williston VT
Gary Paul McClannahan - Rochester MN
John Emery Nordman - Rochester MN
Kevin Gerard Plotz - Byron MN
John Handley Shaffer - Rochester MN
Albert Alfonse Slane - Oronoco MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1100
US Classification:
370231, 370236, 370397, 3482551
Abstract:
A method and Gigabit Ethernet communications adapter are provided for implementing communications in a communications network. A transmission queue is defined of data to be transmitted. A transmission rate is set for the transmission queue. Data to be transmitted are enqueued on the transmission queue. The transmission queue can be subdivided into multiple priority queues, for example, using time wheels, and a transmission rate is set for each transmission queue.

Reusable Configuration Tool

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US Patent:
6536014, Mar 18, 2003
Filed:
Sep 26, 2001
Appl. No.:
09/964300
Inventors:
Gary McClannahan - Rochester MN
John Emery Nordman - Rochester MN
Scott Thomas Senst - Rochester MN
John Shaffer - Rochester MN
Todd Jason Youngman - Rochester MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1750
US Classification:
716 1, 716 5, 716 18
Abstract:
Method, system and signal bearing medium for configuring an integrated circuit are provided. One embodiment provides a method for configuring an integrated circuit, comprising: providing a user interface for displaying one or more abstract data elements for user selection, wherein the one or more abstract data elements represent one or more controls associated with characteristics of the integrated circuit; receiving a user selection of an abstract data element; validating associated abstract rules for the user selected abstract data element; and validating product rules for the one or more product data elements associated with the user selected abstract data element, wherein the one or more product data elements represent one or more controllable features of the integrated circuit.

Exceptions And Interrupts With Dynamic Priority And Vector Routing

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US Patent:
6601122, Jul 29, 2003
Filed:
Apr 17, 2000
Appl. No.:
09/550753
Inventors:
Jonathan W. Byrn - Kasson MN
Chad B. McBride - Rochester MN
Gary P. McClannahan - Rochester MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1324
US Classification:
710266, 710269, 710 50
Abstract:
A method of handling an interrupt request in a computer system by programmably setting an override address associated with a specific interrupt service routine, and servicing an interrupt request based on the override address, which is different from a power-on default address associated with the same interrupt service routine. The method may determine whether the interrupt service routine is critical and, if so, set the override address to a physical location in the on-chip memory of the processing unit, instead of in the off-chip memory (RAM). Override address registers are accessed via the special purpose registers of the processing unit. A validation bit may be turned on in response to the setting of the override address, with both the default address and the override address being provided as separate inputs to a multiplexing device controlled by the validation bit. The override address is forwarded from the multiplexing device to an instruction fetch unit whenever the validation bit has been set. The result is decreased latency associated with interrupt handling, and increased flexibility in user definition of critical versus non-critical interrupts.

Communications Adapter For Implementing Communications In A Network And Providing Multiple Modes Of Communications

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US Patent:
6765911, Jul 20, 2004
Filed:
Feb 3, 1999
Appl. No.:
09/243858
Inventors:
Mark William Branstad - Rochester MN
Jonathan William Byrn - Kasson MN
Gary Scott Delp - Rochester MN
Philip Lynn Leichty - Rochester MN
Todd Edwin Leonard - Williston VT
Gary Paul McClannahan - Rochester MN
John Emery Nordman - Rochester MN
Kevin Gerard Plotz - Byron MN
John Handley Shaffer - Rochester MN
Albert Alfonse Slane - Oronoco MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04L 1256
US Classification:
3703951, 395466
Abstract:
A method and apparatus are provided for implementing communications in a communications network. The apparatus for implementing communications includes a system interface to the communications network. A scheduler schedules enqueued cells and enqueued frames to be transmitted. A segmenter segments frames and cells in into cells or frames applied to a media adaptation block for transmission in a selected one of multiple modes.

Reconfigurable Memory Controller

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US Patent:
7043611, May 9, 2006
Filed:
Dec 11, 2002
Appl. No.:
10/316510
Inventors:
Gary P. McClannahan - Rochester MN, US
Gary S. Delp - Rochester MN, US
George W. Nation - Eyota MN, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 12/00
US Classification:
711154, 711156, 711163, 711170, 326 39
Abstract:
A reconfigurable memory controller includes a plurality of communicatively coupled memory controllers. The plurality of memory controllers may be configured into a first configuration based on a grouping of memory controllers and then reconfigured into a second configuration based on a different grouping of memory controllers, where the first and second configurations have different performance bandwidths for accessing memory.
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Gary P Mcclannahan from Marion, IA, age ~58 Get Report