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Ellie Y Yieh

from San Jose, CA
Age ~59
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Also known as:
Ellie T Yieh, Ellie Y Sullivan
Phone and address:
5888 Pistoia Way, San Jose, CA 95138
Related to:
James L Plumlee, 84Michael J Sullivan, 59Richard L Yieh, 56Sansan San Yieh, 90Cynthia S YiehPaul P Yieh, 57Stanley C Huang, 81Kathleen S Deane, 61
Connected to:
Gary A Yielding, 70Jack A Yielding, 38Kellie M Yielding, 52Lauren J Yien, 31Brandie M Yienger, 38Kevin G Yienger, 62Robert W Yienger, 54Anusak H Yiengpruksawan, 72Aregahegn S Yifru, 52Tedelle Yifru, 73

Ellie Yieh Phones & Addresses

  • 5888 Pistoia Way, San Jose, CA 95138
  • 211 Ventana Ct, Aptos, CA 95003
  • Millbrae, CA
  • Berkeley, CA
  • Santa Clara, CA

Publications

Us Patents

Methods And Apparatus For Depositing Premetal Dielectric Layer At Sub-Atmospheric And High Temperature Conditions

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US Patent:
6348099, Feb 19, 2002
Filed:
Jun 16, 1999
Appl. No.:
09/334437
Inventors:
Li-Qun Xia - Santa Clara CA
Ellie Yieh - Millbrae CA
Srinivas Nemani - San Jose CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
C23C 1600
US Classification:
118697, 118704, 118698, 118684, 118715, 118725, 118728, 700121, 700266, 700282
Abstract:
The present invention provides systems, methods and apparatus for high temperature (at least about 500-800Â C. ) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.

Methods And Apparatus For Shallow Trench Isolation

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US Patent:
6352591, Mar 5, 2002
Filed:
Jul 11, 2000
Appl. No.:
09/613934
Inventors:
Ellie Yieh - Millbrae CA
Li-Qun Xia - Santa Clara CA
Srinivas Nemani - San Jose CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
C23C 1652
US Classification:
118697, 118715, 118725, 700 95, 700108, 700121, 700266, 700275, 700282
Abstract:
The present invention provides systems, methods and apparatus for high temperature (at least about 500-800Â C. ) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.

Sub-Atmospheric Chemical Vapor Deposition System With Dopant Bypass

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US Patent:
6360685, Mar 26, 2002
Filed:
May 5, 1998
Appl. No.:
09/075561
Inventors:
Li-Qun Xia - San Jose CA
Ellie Yieh - Millbrae CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
C23C 1600
US Classification:
118723ME, 118723 MW, 118697, 118695, 156345
Abstract:
A sub-atmospheric chemical vapor deposition (âSACVDâ) system with a bypass from a dopant source to an exhaust system and related methods and devices. The flow of dopant may be established by dumping the dopant flow directly to the foreline of a vacuum exhaust system of an SACVD system, rather than flowing the dopant through the chamber. Establishing the dopant flow in this manner prior to the deposition of a silicon glass film on a substrate allows the initial portion of the silicon glass film to be doped at a higher level. Prior apparatus resulted in a dopant-deficient region of silicon glass formed before the dopant was fully flowing. In one embodiment, a doped silicon glass film is used as a dopant source for a semiconductor material, in another embodiment, a multi-layer doped silicon glass film achieves superior reflow.

Accelerated Plasma Clean

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US Patent:
6374831, Apr 23, 2002
Filed:
Feb 4, 1999
Appl. No.:
09/246036
Inventors:
Shankar N. Chandran - Milpitas CA
Scott Hendrickson - San Jose CA
Gwendolyn D. Jones - Sunnyvale CA
Shankar Venkataraman - Santa Clara CA
Ellie Yieh - Millbrae CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
B08B 700
US Classification:
134 11, 134 1, 134 221, 134 2218, 134902, 438905
Abstract:
A method and apparatus that reduces the time required to clean a processing chamber employing a reactive plasma cleaning process. A plasma is formed in an Astron fluorine source generator from a flow of substantially pure inert-source gas. After formation of the plasma, a flow of a fluorine source gas is introduced therein such that the fluorine source flow accelerates at a rate no greater than 1. 67 standard cubic centimeters per second (scc/s ). In this fashion, the plasma contains a plurality of radicals and dissociated inert-source gas atoms, defining a cleaning mixture. The ratio of inert-source gas to fluorine source is greater than 1:1.

Formation Of A Liquid-Like Silica Layer By Reaction Of An Organosilicon Compound And A Hydroxyl Forming Compound

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US Patent:
6413583, Jul 2, 2002
Filed:
Jun 22, 1999
Appl. No.:
09/338470
Inventors:
Farhad K. Moghadam - Los Gatos CA
David W. Cheung - Foster City CA
Ellie Yieh - San Jose CA
Li-Qun Xia - San Jose CA
Chi-I Lang - Sunnyvale CA
Shin-Puu Jeng - Hsinchu, TW
Frederic Gaillard - Voiron, FR
Shankar Venkataraman - Santa Clara CA
Srinivas Nemani - Milpitas CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
C23C 1640
US Classification:
42724915, 42725537, 427579, 438790, 438789, 438787, 438763
Abstract:
A method for depositing silicon oxide layers having a low dielectric constant by reaction of an organosilicon compound and a hydroxyl forming compound at a substrate temperature less than about 400Â C. The low dielectric constant films contain residual carbon and are useful for gap fill layers, pre-metal dielectric layers, inter-metal dielectric layers, and shallow trench isolation dielectric layers in sub-micron devices. The hydroxyl compound can be prepared prior to deposition from water or an organic compound. The silicon oxide layers are preferably deposited at a substrate temperature less than about 40Â C. onto a liner layer produced from the organosilicon compound to provide gap fill layers having a dielectric constant less than about 3.

Method Of Reducing Undesired Etching Of Insulation Due To Elevated Boron Concentrations

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US Patent:
6426015, Jul 30, 2002
Filed:
Dec 14, 1999
Appl. No.:
09/461504
Inventors:
Li-Qun Xia - Santa Clara CA
Francimar Campana - Milpitas CA
Ellie Yieh - San Jose CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
B44C 122
US Classification:
216 62, 216 67, 134 221, 438424, 438428, 438433, 438778, 438783, 438789
Abstract:
A method is provided for reducing elevated boron concentrations (denoted as âboron spikesâ) in an insulating layer containing silicon, boron and other elements where the layer interfaces with surfaces of a semiconductor device. The method includes the steps of: seasoning a reaction chamber by flowing into it a mixture of gasses containing silicon, boron, ozone and other elements in predetermined proportions under set conditions of time, pressure, temperature and flow rates to deposit on inner walls and surfaces of the chamber a thin seasoning coating, and placing a semiconductor device in the chamber and covering it with an insulating layer having a composition similar to the seasoning coating. Subsequent etching of selected portions of the insulating layer has been found not to expose conductive surfaces of the device.

Dual Frequency Plasma Enhanced Chemical Vapor Deposition Of Silicon Carbide Layers

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US Patent:
6465366, Oct 15, 2002
Filed:
Sep 12, 2000
Appl. No.:
09/660268
Inventors:
Srinivas Nemani - San Jose CA
Li-Qun Xia - Santa Clara CA
Ellie Yieh - San Jose CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 2131
US Classification:
438778
Abstract:
A method for forming a silicon carbide layer for use in integrated circuit fabrication is disclosed. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and an inert gas in the presence of an electric field. The electric field is generated using mixed frequency radio frequency (RF) power. The silicon carbide layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the silicon carbide layer is used as a hardmask for fabricating integrated circuit structures such as, for example, a damascene structure. In another integrated circuit fabrication process, the silicon carbide layer is used as an anti-reflective coating (ARC) for DUV lithography.

Surface Treatment Of C-Doped Sio2 Film To Enhance Film Stability During O2 Ashing

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US Patent:
6465372, Oct 15, 2002
Filed:
Aug 7, 2000
Appl. No.:
09/633495
Inventors:
Li-Qun Xia - Santa Clara CA
Frederic Gaillard - Voiron, FR
Ellie Yieh - San Jose CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 2131
US Classification:
438787, 438789, 438790, 438758
Abstract:
A method for forming an insulation layer over a substrate. The method forms a carbon-doped silicon oxide layer by thermal chemical vapor deposition using an organosilane. The carbon-doped silicon oxide layer is subsequently cured and densified. In one embodiment, the cured film is densified in a nitrogen-containing plasma. The method is particularly suitable for deposition of low dielectric constant films, i. e. , where k is less than or equal to 3. Low-k, carbon-doped silicon oxide methylsilane or di-, tri-, tetra-, or phenylmethylsilane. and ozone. The above method can be carried out in a substrate processing system having a process chamber; a substrate holder, a heater, a gas delivery system, and a power supply, all of which are coupled to a controller. The controller contains a memory having a computer-readable medium with a program embodied for directing operation of the system in accordance with above method.
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Ellie Y Yieh from San Jose, CA, age ~59 Get Report