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Dinesh D Jayabharathi

from Irvine, CA
Age ~56
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Also known as:
Dinesh Tr Jayabharathi Jayabharathi, Dinesh M Jayabharathi, Dinesh T Jayabharathi, Dinesh C Jayabharathi, Dinesa Jayabharathi, Srinivasulu Alampally, Dinesh I
Related to:
Aishwarya H Jayabharathi, 27Krishnaleela Narayanababu, 56
Connected to:
Amit Jayachandran, 48Anoop C Jayachandran, 45Arun Jayachandran, 50Bhavani Jayachandran, 55Jayashree Jayachandran, 47Prashanth Jayachandran, 37Rohith M Jayachandran, 46Gopinath Jayagopal, 53Chaminda N Jayakody, 46Don C Jayakody, 69

Dinesh Jayabharathi Phones & Addresses

  • Irvine, CA
  • Los Angeles, CA
  • 5351 E Rural Ridge Cir, Anaheim, CA 92807 (714) 538-1583
  • Tustin, CA
  • 7843 E Teal Ln, Orange, CA 92869
  • Mission Viejo, CA
  • Santa Ana, CA
  • Sunnyvale, CA
  • San Jose, CA
  • Santa Clara, CA
  • 2274 Juniper Rd, Tustin, CA 92780

Work

Company: Broadcom Jul 2007 Position: R&d engineering

Education

Degree: MBA School / High School: University of Phoenix 2005 to 2008

Skills

ASIC • Static Timing Analysis • TCL • Semiconductors • Verilog • DFT • Silicon debug • Debugging • Project Management

Languages

Tamil • English

Industries

Consumer Electronics

Resumes

Resumes

Dinesh Jayabharathi Photo 1

Engineering At Broadcom

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Position:
R&D Engineering at Broadcom
Location:
Orange County, California Area
Industry:
Consumer Electronics
Work:
Broadcom since Jul 2007
R&D Engineering
Marvell Semiconductors Nov 2005 - Jul 2007
R&D Engineering
QLogic Corporation Oct 1998 - Nov 2005
Principal Engineer
Unisys Corporation Aug 1992 - Oct 1998
Staff Engineer
Education:
University of Phoenix 2005 - 2008
MBA Southern Illinois University, Carbondale 1989 - 1991
PSG College of Technology 1985 - 1989
BE, Electronics and Communication Engineering
Skills:
ASIC
Static Timing Analysis
TCL
Semiconductors
Verilog
DFT
Silicon debug
Debugging
Project Management
Languages:
Tamil
English

Publications

Us Patents

System And Method For Conducting Bist Operations

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US Patent:
7240267, Jul 3, 2007
Filed:
Nov 8, 2004
Appl. No.:
10/983944
Inventors:
Dinesh Jayabharathi - Orange CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G01R 31/28
US Classification:
714733
Abstract:
Method and system for initiating a built in self test (“BIST”) operation for memory modules is provided. The method includes, determining if a test access port (“TAP”) controller instruction or an internal register control bit are to be used for initiating the BIST operation; sending the internal register control bit to a memory BIST controller for initiating the BIST operation; and setting a status bit in the internal register after the BIST operation is complete. The system includes a storage controller with an internal register for setting a control bit for initiating a BIST operation; a test access port (“TAP”) controller for sending an instruction to a memory BIST controller to initiate a BIST operation; and a multiplexer for selecting between the control bit and the instruction for initiating the BIST operation.

Integrated Memory Controller

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US Patent:
7286441, Oct 23, 2007
Filed:
Oct 4, 2006
Appl. No.:
11/542862
Inventors:
Theodore C. White - Rancho Santa Margarita CA, US
Dinesh Jayabharathi - Orange CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G11C 8/00
US Classification:
365233, 365193
Abstract:
A memory system comprises a memory that includes at least one of Synchronous Dynamic Random Access Memory (SDRAM) and Double Data Rate SDRAM (DDR). A memory controller communicates with the memory, generates an SDRAM clock signal, and receives a bi-directional sampling clock signal (DQS). When the memory includes the DDR, the memory generates the DQS. When the memory includes the SDRAM, the DQS is based on the SDRAM clock signal.

System And Method For Using Tap Controllers

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US Patent:
7526691, Apr 28, 2009
Filed:
Oct 15, 2003
Appl. No.:
10/686151
Inventors:
Dinesh Jayabharathi - Orange CA, US
William W. Dennin - Mission Viejo CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G01R 31/317
G01R 31/40
US Classification:
714724, 714726
Abstract:
A system and method for dynamically writing to and reading from an internal register space of a chip using a TAP controller without interfering with the normal operation of the chip is provided. Data that is to be written is loaded into a data register in the TAP controller before being written in the internal register space and the write instructions are loaded into an instruction register of the TAP controller. The address of the internal register space from where data is to be read is also loaded to the data register. Data is read and/or written from the internal register space after the TAP controller gets access to the internal register space via arbitration.

Integrated Memory Controller

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US Patent:
7535791, May 19, 2009
Filed:
Oct 23, 2007
Appl. No.:
11/977169
Inventors:
Theodore C. White - Rancho Santa Margarita CA, US
Dinesh Jayabharathi - Orange CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G11C 8/00
US Classification:
36523313, 365194
Abstract:
A memory system includes Synchronous Dynamic Random Access Memory (SDRAM) A memory controller communicates with the memory, generates an SDRAM clock signal, that receives a bi-directional sampling clock signal (DQS) that is generated based on the SDRAM clock signal, and reads data from the memory based on the DQS.

Integrated Memory Controller

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US Patent:
7596053, Sep 29, 2009
Filed:
Oct 4, 2006
Appl. No.:
11/542726
Inventors:
Theodore C. White - Rancho Santa Margarita CA, US
Dinesh Jayabharathi - Orange CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G11C 11/00
US Classification:
3652335, 365194
Abstract:
A circuit for reading data from a buffer memory, which is Synchronous Dynamic Random access Memory (“SDRAM”), or Double Data Rate-Synchronous Dynamic Random Access Memory (“DDR”) comprises logic for managing programmable clock signal relationships such that data that is read from the DDR is centered within a DQS signal which is generated from the DDR and then appropriately delayed.

System And Method For Conducting Bist Operations

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US Patent:
8015448, Sep 6, 2011
Filed:
Jun 19, 2007
Appl. No.:
11/820226
Inventors:
Dinesh Jayabharathi - Orange CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 11/00
US Classification:
714 30, 714 42, 714733
Abstract:
A storage controller including a first controller. The first controller includes a memory module, a test access port controller, the test access port controller configured to control a built in self-test operation on the memory module, and a register configured to store a first instruction. In response to the storage controller detecting a test access port interface being accessible to the storage controller, the test access port controller is configured to control the built in self-test operation on the memory module of the first controller by having either (i) a second instruction sent from the test access port controller to the first controller or (ii) the first instruction sent from the register to the first controller. The first controller is configured to perform the built in self-test operation on the memory module in response to having received the first instruction or having received the second instruction.

Integrated Memory Controller

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US Patent:
20050276151, Dec 15, 2005
Filed:
Jun 14, 2004
Appl. No.:
10/867113
Inventors:
Theodore White - Rancho Santa Margarita CA, US
Dinesh Jayabharathi - Orange CA, US
International Classification:
G11C008/00
US Classification:
365233000
Abstract:
A system and circuit for reading and writing data to a buffer memory, which is Synchronous Dynamic Random access Memory (“SDRAM”), or Double Data Rate-Synchronous Dynamic Random Access Memory (“DDR”) is provided. The circuit includes logic for managing programmable clock signal relationships such that data arrives at an optimum time for writing. Data that is to be written at DDR is moved from a first buffer clock to a DDR write clock signal and to a DQS signal that is based on a SDRAM clock signal. Also, plural tap-cells may be used to delay clock signals such that data and clock signals are aligned. An emulated DQS signal in a DDR capture scheme is used for reading from a SDRAM.
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Dinesh D Jayabharathi from Irvine, CA, age ~56 Get Report