Dinesh J Alladi

8169243, May 1, 2012

Apr 2, 2009

12/417497

Xiaohong Quan - San Diego CA, US
Tongyu Song - San Diego CA, US
Lennart Mathe - San Diego CA, US
Dinesh J. Alladi - San Diego CA, US

Qualcomm Incorporated - San Diego CA

H03L 7/06

327158, 327149

Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. In a further aspect, the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non-overlapping time (t) that is independent of manufacturing process variations.

8564346, Oct 22, 2013

Jan 23, 2012

13/356187

Xiaohong Quan - San Diego CA, US
Tongyu Song - San Diego CA, US
Lennart Mathe - San Diego CA, US
Dinesh J. Alladi - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

H03L 7/06

327158, 327149

Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. A non-overlapping clock generation circuit comprises a delay lock loop (DLL) circuit that generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. The clock generator circuit may also include voltage-controlled delay cells that generate sets of clock signals delayed from one another by a non-overlapping time (t).

20100283522, Nov 11, 2010

May 6, 2009

12/436288

Xiaohong Quan - San Diego CA, US
Lennart K. Mathe - San Diego CA, US
Liang Dai - San Diego CA, US
Dinesh J. Alladi - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

H03K 3/017

327175

All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block is provided for computing the product of a selected duty cycle and a discrete ratio between a reference clock period and a high-frequency oscillator period. The computation block may be coupled to a pulse width generator for generating signals having pulse widths that are integer multiples of the high-frequency oscillator period. In another aspect, a pulse width generator may also accommodate mixed fractional multiples of high-frequency oscillator periods by tapping the individual inverter stages of a delay line matched to the individual inverter stages of a ring oscillator exemplary embodiment of the high-frequency oscillator.

20220368299, Nov 17, 2022

May 13, 2021

17/320077

- San Diego CA, US
Aram Akhavan - San Diego CA, US
Ganesh Kiran - San Diego CA, US
Lei Sun - San Diego CA, US
Elias Dagher - Laguna Niguel CA, US
Dinesh Jagannath Alladi - San Diego CA, US

H03G 3/30
H03M 1/12
H03F 3/19
H03F 3/21

An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain- stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.

20220311460, Sep 29, 2022

Mar 24, 2021

17/211769

- San Diego CA, US
Li LU - San Diego CA, US
Anees HABIB - Mountain View CA, US
Chinmaya MISHRA - San Diego CA, US
Damin CAO - San Diego CA, US
Arul BALASUBRAMANIYAN - Plano TX, US
David Ta-hsiang LIN - San Diego CA, US
Shuang ZHU - San Diego CA, US
Dinesh Jagannath ALLADI - San Diego CA, US

H04B 1/04
H03M 1/46
H03M 3/00

Aspects of the disclosure relate to an apparatus for wireless communication. The apparatus may include a set of power detectors configured to generate a set of analog signals related to a set of output signal power levels of a set of transmit chains of a transmitter, respectively; an analog summer; a set of switching devices configured to send a selected one or more of the set of analog signals to the analog summer, and substantially isolated unselected one or more of the set of power detectors from the analog summer, wherein the analog summer is configured to generate a cumulative analog signal based on a sum of the selected one or more of the set of analog signals; an analog-to-digital converter (ADC) configured to generate a digital signal based on the cumulative analog signal; and a controller configured to control the set of switching devices.

20230100825, Mar 30, 2023

Sep 24, 2021

17/484581

- San Diego CA, US
Lei Sun - San Diego CA, US
Yuhua Guo - San Diego CA, US
Elias Dagher - Laguna Niguel CA, US
Aram Akhavan - San Diego CA, US
Yan Wang - San Diego CA, US
Dinesh Jagannath Alladi - San Diego CA, US

H03M 1/16
H03M 1/38

An apparatus is disclosed for pipelined analog-to-digital conversion. In an example aspect, the apparatus includes a pipelined analog-to-digital converter (ADC). The pipelined ADC includes a first stage and a second stage. The first stage includes a sampler and a quantizer coupled to the sampler. The first stage also includes a current distribution circuit coupled to the sampler. The second stage includes a sampler coupled to the current distribution circuit and a quantizer coupled to the sampler of the second stage.

20200333819, Oct 22, 2020

Mar 31, 2020

16/835494

- San Diego CA, US
Dinesh Jagannath ALLADI - San Diego CA, US
Kentaro YAMAMOTO - San Diego CA, US
Sean BAKER - San Diego CA, US
Liang ZHAO - Saratoga CA, US

G05F 3/08

An apparatus for generating a substantially constant DC reference voltage. The apparatus includes a reference voltage generator configured to generate a substantially constant direct current (DC) reference voltage based on a voltage on a data signal transmission line, wherein the voltage is based on a bandgap reference voltage. In one implementation, the data signal transmission line is a differential signal transmission line and the voltage is a common mode voltage. In another implementation, the data signal transmission line is an I-data signal transmission line and a Q-data signal transmission line, and the voltage is an average or weighted-average of the common mode voltages of the I- and Q-differential signals. In another implementation, the reference voltage is based on a single-ended (e.g., positive- and/or negative)-component or vice-versa of I- and Q-data signals, respectively.

20190334539, Oct 31, 2019

Apr 25, 2018

15/962967

- San Diego CA, US
Yuhua GUO - San Diego CA, US
Lai Kan LEUNG - San Marcos CA, US
Elias DAGHER - Laguna Niguel CA, US
Dinesh Jagannath ALLADI - San Diego CA, US

H03M 1/12
H04B 1/16

A receiver may include a time-interleaved charge sampler comprising a charge sampler switch in series with a charge sampler capacitor. The receiver may also include a current buffer configured to drive the time-interleaved charge sampler.