Damodar R Thummalapally

6766317, Jul 20, 2004

Jul 18, 2001

09/908987

Mohit Sharma - Bangalore, IN
Damodar Reddy Thummalapally - Milpitas CA
Tavare Dhanaraj B. - Maharashta, IN

Alliance Semiconductor - Santa Clara CA

G06F 1730

707 3, 707 2, 707 4, 707 5, 365 49, 36518525

A range check array structure for searching and comparing external data from an external search data key is disclosed. The structure has data storage means with at least one of an upper limit field, and a lower limit field, and one or more bit lines running therethrough for transmitting an input data word for comparison with the stored data word range. The input data word being compared with a respective stored data word to detect a match that is indicated along a match line by the check array structure. The check array structure further includes a range match detection means connected to the match line to determine the match or mismatch of the applied data stream with the stored data in each range check cell.

6839799, Jan 4, 2005

Jul 17, 2001

09/908483

Pamela Kumar - Bangalore, IN
Mohit Sharma - Bangalore, IN
Damodar Reddy Thummalapally - Milpitas CA, US
Tavare Dhanaraj B. - Maharashta, IN

Alliance Semiconductor - Santa Clara CA

G06F 1200

711108, 365 49

A method is provided for prioritizing the entries in a database, where each entry is composed of multiple dimensions. Prioritization is required when there are multiple matches in the database. The number of matches can be the same as the number of entries in the database. To prioritize such a huge number of entries in a minimum number of clock cycles, a distributed prioritizer is implemented by partitioning stored binary data into half nibbles comprising of two bits of data each. Each half nibble is encoded into an expanded format allotting priority value to the stored encoded half nibbles. The stored encoded half nibbles are compared across a word array to determine an exact match.

7629812, Dec 8, 2009

Aug 3, 2007

11/888977

Damodar R. Thummalapally - Milpitas CA, US
Abhijit Ray - Sunnyvale CA, US

DSM Solutions, Inc. - Los Gatos CA

H03K 19/173

326 38, 326 40

A switching circuit can have a plurality of first signal lines of a programmable logic device, a plurality of second signal lines of the programmable logic device, and a plurality of switch elements. Each switch element can selectively couple one first signal line to a second signal line and include one or more switch junction field effect transistors (JFETs) having a first control gate separated from a second control gate by a channel region.

7633784, Dec 15, 2009

May 17, 2007

11/804132

Damodar R. Thummalapally - Milpitas CA, US

DSM Solutions, Inc. - Los Gatos CA

G11C 15/00

365 4912, 365 491, 365 4911, 365 4917

A semiconductor memory device including a dynamic random access memory (DRAM) cell and a ternary content addressable memory (TCAM) cell is disclosed. The DRAM cell may include a data storing portion and a data read portion. The data storing portion and data read portion comprising p-channel junction field effect transistors. The TCAM cell including an x-cell, y-cell, and comparator circuit. The x-cell, y-cell, and comparator circuits comprising p-channel JFETs.

7646233, Jan 12, 2010

Jul 28, 2006

11/495908

Damodar R. Thummalapally - Milpitas CA, US
Richard K. Chou - Palo Alto CA, US

DSM Solutions, Inc. - Los Gatos CA

H03K 3/01

327536, 327534, 327333

A level shifting circuit can include a first driver junction field effect transistor (JFET) having a source coupled to a reference supply node and a second driver JFET of a second conductivity type having a source coupled to a boosted supply node, and a first charge pump circuit. The first charge pump circuit can be coupled between the first driver control node and an input node coupled to receive an input signal, and can couple a first terminal of a first capacitor between a reference supply node and a power supply node in response to an input signal. The power supply node can be coupled to receive a power supply potential, the reference supply node can be coupled to receive a reference potential, and the boosted power supply node can be coupled to receive a boosted potential. The reference potential can be between the power supply potential and the boosted potential.

7694069, Apr 6, 2010

Mar 29, 2007

11/693441

Damodar R. Thummalapally - Milpitas CA, US

DSM Solutions, Inc. - Los Gatos CA

G06F 13/00

711108, 711113

A system for identifying asserted signals includes a plurality of input ports, a priority encoding module, and a match module. The plurality of input ports receive one of a plurality of input signals. The priority encoding module is coupled to the plurality of input ports and outputs a signal indicating a highest-priority input signal that is asserted. The match module is also coupled to the plurality of input ports and receives a plurality of match detect signals from the priority encoding module. Each match detect signal is associated with a particular input signal and indicates whether another input signal having a higher-priority than the associated input signal is asserted. The match module also generates a multiple match signal based on the input signals and the match detect signals. The multiple match signal indicates whether more than one of the input signals is asserted.

7729149, Jun 1, 2010

May 1, 2007

11/799305

Damodar R. Thummalapally - Milpitas CA, US

SuVolta, Inc. - Los Gatos CA

G11C 15/00

365 491, 365 4917, 365174

A semiconductor device that includes a memory cell having a junction field effect transistor (JFET) used to form a content addressable memory (CAM) cell is disclosed. The JFET may include a data storage region disposed between a first and second insulating region. The data storage region provides a first threshold voltage to the JFET when storing a first data value and provides a second threshold voltage to the JFET when storing a second data value. The memory cell is a dynamic random access memory (DRAM) cell and can be used to form a CAM cell. The CAM cell may be a ternary CAM cell formed with as few as two JFETs.

7746146, Jun 29, 2010

Sep 1, 2006

11/515252

Richard K. Chou - Palo Alto CA, US
Damodar R. Thummalapally - Milpitas CA, US

SuVolta, Inc. - Los Gatos CA

H03L 5/00

327333, 326 80

A level shifting circuit can include a first input junction field effect transistor (JFET) having a gate coupled to receive an input signal having a first voltage swing that provides a controllable impedance path between a first supply node and a first terminal of a first bias stack including at least one JFET. A driver circuit can be coupled to receive an output from the first bias stack that provides a level shifted output having a second voltage swing that is less than the first voltage swing.