Chetan M Prasad

20080076216, Mar 27, 2008

Sep 25, 2006

11/527263

Sangwoo Pae - Beaverton OR, US
Jose Maiz - Portland OR, US
Chetan Prasad - Hillsboro OR, US

H01L 21/336

438257

Semiconductor devices and methods to fabricate thereof are described. For an embodiment, a semiconductor device features a double capping layer. The double capping layer may include a first-capping layer and a second-capping layer. The first-capping layer protects a high-k gate dielectric film during a replacement gate process and the second-capping layer protects the first-capping layer during metal deposition. For other embodiments, the first-capping layer prevents the interaction between a polysilicon layer and a high-k gate dielectric film to prevent V-pinning of fabricated transistors.

20100164603, Jul 1, 2010

Dec 30, 2008

12/319104

Walid M. Hafez - Portland OR, US
Chia-Hong Jan - Portland OR, US
Chetan Prasad - Hillsboro OR, US
Sangwoo Pae - Beaverton OR, US
Zhanping Chen - Portland OR, US
Anisur Rahman - Hiilsboro OR, US

H01H 37/76
H01L 29/00

327525, 257530, 257E29001

A programmable anti-fuse element includes a substrate (), an N-well () in the substrate, an electrically insulating layer () over the N-well, and a gate electrode () over the electrically insulating layer. The gate electrode has n-type doping so that the N-well is able to substantially contain within its boundaries a current generated following a programming event of the programmable anti-fuse element. In the same or another embodiment, a twice-programmable fuse element () includes a metal gate fuse () and an oxide anti-fuse () such as the programmable anti-fuse element just described.