Inventors:
Steve K. Hsia - Saratoga CA
Pritpal S. Mahal - San Jose CA
Wei-Ren Shih - San Jose CA
Assignee:
Catalyst Semiconductor, Inc. - Santa Clara CA
International Classification:
H01L 2710
H01L 2978
Abstract:
A process is disclosed for producing a high density split gate nonvolatile memory cell which includes a floating gate and a control gate that is formed above the floating gate. The drain region is self-aligned to the floating gate and the source region is self-aligned to the control gate. Fully self-aligned implantation is made possible by the process and structure using self-aligned etch. Programming of the memory cell uses standard EPROM programming, and erasing is accomplished by Fowler-Nordheim tunneling or photoemission. The memory cell can be made with a reduced cell size and read current uniformity is obtained.