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Loi T Le

from San Jose, CA
Age ~65
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Also known as:
Loi Narcie Le, Le Quyen Le, Le Loi, Le Le-Quyen
Related to:
Khanh L Yen, 34Davis Le Huynh, 48Le Loi T, 65Thu T Le, 63Hoang T Le, 62Joselyn Le, 27David Le, 55Quyen Le, 29Nguyet M Le, 56Thuy T Le, 67Daisy Le, 71
Connected to:
Aimy T Le, 33Al T Le, 45Alen D Le, 42Alena Le, 28Amanda Le, 54Ananda T Le, 38Anastasia Le, 27Angie Le, 72Anhdao Le, 45Annah M Le, 41

Loi Le Phones & Addresses

  • San Jose, CA
  • Berkeley, CA
  • Milpitas, CA

Resumes

Resumes

Loi Le Photo 1

Loi Le

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Location:
San Francisco, CA
Industry:
Semiconductors
Education:
San Jose State University 1997
Bachelors, Bachelor of Science, Electrical Engineering
Loi Le Photo 2

Loi Le

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Loi Le Photo 3

Loi Le

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Loi Le Photo 4

Loi Le

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Loi Le Photo 5

Engineer At Lam Research

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Position:
Engineer at Lam Research
Location:
San Francisco Bay Area
Industry:
Electrical/Electronic Manufacturing
Work:
Lam Research
Engineer

Publications

Us Patents

Power Down Circuit For High Output Impedence State Of I/O Driver

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US Patent:
20030071660, Apr 17, 2003
Filed:
Oct 15, 2001
Appl. No.:
09/978255
Inventors:
Loi Le - San Jose CA, US
Pekka Ojala - Fremont CA, US
Bahram Fotouhi - Cupertino CA, US
Assignee:
Exar Corporation - Fremont CA
International Classification:
H03B001/00
US Classification:
327/108000
Abstract:
A circuit for putting an output driver into a high impedance state upon failure of the power supply. This is accomplished by providing a first transistor that is connected between the power supply and the n-well to charge the n-well node of the PMOS drive transistor. Upon failure of the supply voltage, a number of transistors are connected to couple the n-well and a gate of the PMOS drive transistor to the output line, so that they track the voltage level of the output, thereby preventing forward biasing of the P+/n-well diode.
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Loi T Le from San Jose, CA, age ~65 Get Report