Byeong G Kim

6404000, Jun 11, 2002

Jun 22, 2000

09/599261

Rama Divakaruni - Somers NY
Rajarao Jammy - Wappingers Falls NY
Byeong Y. Kim - Lagrangeville NY
Jack A. Mandelman - Stormville NY
Akira Sudo - Poughkeepsie NY
Dirk Tobben - Dresden, DE

International Business Machines Corporation - Armonk NY
Infineon Technologies North America Corp. - San Jose CA
Kabushiki Kaisha Toshiba - Kawasaki

H01L 2972

257296, 257301, 257302, 257304, 257305

A memory structure having a trenched formed in a substrate. A collar oxide is located in an upper portion of the trench and includes a pedestal portion. A method of forming a memory device having a collar oxide with pedestal collar is also disclosed.

6656817, Dec 2, 2003

Apr 30, 2002

10/136097

Ramachandra Divakaruni - Ossining NY
Laertis Economikos - Wappingers Falls NY
Byeong Y. Kim - LaGrangeville NY

International Business Machines Corporation - Armonk NY

H01L 2176

438435

Disclosed herein is a method of filling isolation trenches in a substrate. The method includes anisotropically etching trenches in a surface of a substrate and partially filling the trenches with a deposited oxide. As a consequence of the deposition, the oxide accumulates in mounds on the surface between trenches. The trenches are then filled with a supporting material of a highly flowable material such as anti-reflective coating (ARC), low-K dielectric, or a spin-on-polymer, or alternatively, a supporting material of polysilicon. A flattening process is then applied to lower the mound topography. The supporting material is then removed and the filling of the trenches with oxide is then continued. When polysilicon is used as the supporting material, the mounds are removed by wet etching prior to removing the polysilicon.

7601646, Oct 13, 2009

Jul 21, 2004

10/710566

Ramachandra Divakaruni - Ossining NY, US
Hiroyuki Akatsu - Yorktown Heights NY, US
George Worth - Gardiner NY, US
Jay Strane - Chester NY, US
Byeong Kim - Chester NY, US

International Business Machines Corporation - Armonk NY

H01L 21/3065
H01L 21/308
H01L 21/311

438697, 257E21245

Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.

20130183806, Jul 18, 2013

Mar 7, 2013

13/788406

International Business Machines Corporation - Armonk NY, US
Kangguo Cheng - Albany NY, US
Joseph Ervin - Hopewell Junction NY, US
David M. Fried - Brewster NY, US
Byeong Y. Kim - Lagrangeville NY, US
Chengwen Pei - Danbury CT, US
Ravi M. Todi - San Diego CA, US
Geng Wang - Stormville NY, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

H01L 29/92

438388

In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.

20180331047, Nov 15, 2018

Jul 23, 2018

16/041878

- Armonk NY, US
Allen H. Gabor - Katonah NY, US
Sivananda K. Kanakasabapathy - Niskayuna NY, US
Byeong Y. Kim - Lagrangeville NY, US
Fee Li Lie - Albany NY, US
Stuart A. Sieg - Albany NY, US

H01L 23/544
H01L 21/308
G03F 7/20
H01L 21/033
H01L 21/311
G03F 9/00

Methods of forming a registration mark may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.

20180061773, Mar 1, 2018

Oct 26, 2017

15/794637

- Armonk NY, US
Allen H. Gabor - Katonah NY, US
Sivananda K. Kanakasabapathy - Niskayuna NY, US
Byeong Y. Kim - Lagrangeville NY, US
Fee Li Lie - Albany NY, US
Stuart A. Sieg - Albany NY, US

H01L 23/544
H01L 21/308
G03F 9/00
G03F 7/20
H01L 21/311
H01L 21/033

Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.

20160358861, Dec 8, 2016

Aug 17, 2016

15/239166

- Armonk NY, US
Allen H. Gabor - Katonah NY, US
Sivananda K. Kanakasabapathy - Niskayuna NY, US
Byeong Y. Kim - Lagrangeville NY, US
Fee Li Lie - Albany NY, US
Stuart A. Sieg - Albany NY, US

H01L 23/544
H01L 21/311
H01L 21/308

Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.

20160247766, Aug 25, 2016

Feb 25, 2015

14/630715

- Armonk NY, US
Allen H. Gabor - Katonah NY, US
Sivananda K. Kanakasabapathy - Niskayuna NY, US
Byeong Y. Kim - Lagrangeville NY, US
Fee Li Lie - Albany NY, US
Stuart A. Sieg - Albany NY, US

H01L 23/544
H01L 21/033
H01L 21/311

Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.