Kyung H Lee

6413557, Jul 2, 2002

May 30, 2000

09/580977

Kyung Ja Lee - Forest Hills NY, 11375

A61K 3578

424757, 426634, 426507, 426508, 426656

A soy-containing nutritional supplement is disclosed which contains high amounts of soy protein, phytonutrients, and soluble and insoluble types of fiber.

6501302, Dec 31, 2002

Oct 15, 2001

09/977770

Kyung T. Lee - Santa Clara CA
Jason M. Hart - Santa Clara CA

Sun Microsystems, Inc. - Santa Clara CA

G01R 1500

327 55, 327 57

A single-input/dual output sense amplifier includes cross-coupled transistors connected to a reference voltage; a first input transistor and a second input transistor connected to the cross-coupled transistors, wherein the first input transistor is coupled to a single input bit-line and the second input transistor is coupled to a reference voltage; an inverter receiving the input bit-line signal and outputting a complement of the input bit-line signal; a control circuit coupled to the second input transistor and receiving the complement of the input bit-line signal, wherein the cross-coupled transistors produce dual differential outputs. A method of producing dual differential output signals from a single input signal includes receiving a single input bit-line signal; inverting the received single input bit-line signal to produce the complement of the received single input bit-line signal; controlling the charging and discharging of a reference node based on the complement of the received input bit-line signal; and outputting dual differential output signals based on the single input bit-line signal and the reference node.

D476588, Jul 1, 2003

Jun 28, 2002

29/163186

Kyung Sang Lee - Oakland Gardens NY, 11364-2429

1005

D10104

6594679, Jul 15, 2003

Mar 20, 2000

09/531850

Kyung Tek Lee - Sunnyvale CA
Kevin John Nowka - Round Rock TX
Sang Hoo Dhong - Austin TX

International Business Machines Corporation - Armonk NY

G06F 1500

708211

A leading-zero anticipator having an independent sign bit determination module is disclosed. An apparatus for anticipating leading zeros for an adder within a floating-point processor includes a leading-zero anticipator and a sign determination module. The leading-zero anticipator generates a leading zeros string and a leading ones string by examining carry propagates, generates, and kills of two adjacent bits of two input operands of the adder. The leading zeros string is intended for a positive sum, and the leading ones string is intended for a negative sum. Independent of the leading-zero anticipator, the sign determination module determines a sign of the output of the adder in concurrence with the operations within the leading-zero anticipator.

6766264, Jul 20, 2004

Aug 2, 2002

10/211681

Dae Suk Jung - Santa Clara CA
Kyung Lee - Santa Clara CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 1100

702107, 702191, 716 4

One embodiment of the present invention provides a system for calibrating a model of a digital circuit to account for noise effects between signal lines. The system operates by first fabricating a digital circuit for calibration purposes. Next, an input signal is applied to an aggressor net within the digital circuit. The system then measures how noise from the input signal affects the amplitude of a signal on a victim net within the digital circuit. Finally, the system adjusts parameters of the circuit model using the measured results.

6774781, Aug 10, 2004

Aug 20, 2002

10/224965

Kyung Sang Lee - Bayside NY, 11364

B60Q 126

340468, 3404571, 180273, 180268

A safety light for use in vehicles is disclosed. The safety light would comprise a brake light and a seat belt signal light. The brake light would function as a normal window-mounted brake light would function, with the seat belt signal light functioning when a driver does not have their seat belt properly installed.

7256619, Aug 14, 2007

Apr 4, 2005

11/099186

Yonghee Im - Pleasanton CA, US
Kyung T. Lee - San Jose CA, US
Han Bin Kim - Pleasanton CA, US

Sun Microsystems, Inc. - Santa Clara CA

H03K 19/096
H03K 19/20

326 95, 326121, 365203, 327544

A method and apparatus for shifting a dynamic circuit, driven by a one-shot clock, to a pre-charge mode, during a power-off mode, is provided. Under certain conditions, a floating node may be present in a dynamic circuit. One approach to prevent floating nodes involves the generation of a new one-shot clock signal that is supplied to the last dynamic circuit in the series of dynamic circuits before the output flop (“the final dynamic circuit”). The new one-shot clock signal is driven to a logical low value when the power-off signal has a logical high value. Another approach to prevent floating nodes involves modifying the final dynamic circuit to include a structure that, when the power-off signal has a logical high value, drives the dynamic node to either a logical high value or a logical low value to prevent the dynamic node from becoming a floating node.

20080109479, May 8, 2008

Apr 1, 2004

10/551661

Lewis Cheng - Mountain View CA, US
Joseph Fusion - Portland OR, US
Kyung Lee - Fort Lee NJ, US

Plantii USA, Inc., - San Jose CA

G06F 17/30

7071041, 707E17122

Provided herein is a system, method and computer program product for effectively arranging and rendering multimedia information using for example, Macromedia's Flash™ technology, the Extensible Markup Language (XML) language and the Mathematical Markup Language (MathML). The invention utilizes question data (), possible visual aids (), possible descriptive solutions (), and element alignment ().