Zhonghai Shi

7556992, Jul 7, 2009

Jul 31, 2006

11/496106

Zhonghai Shi - Austin TX, US
Ted R. White - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/00
H01L 21/84

438164, 438259, 257E21561

A method is provided for making a semiconductor device, comprising (a) providing a semiconductor stack comprising a first semiconductor layer () having a crystallographic orientation and a second semiconductor layer () having a crystallographic orientation; (b) defining an oxide mask () in the first semiconductor layer; and (c) utilizing the oxide mask to pattern the second semiconductor layer.

7761838, Jul 20, 2010

Sep 26, 2007

11/861492

Zhonghai Shi - Austin TX, US
Mark Michael - Cedar Park TX, US
Donna Michael, legal representative - Cedar Park TX, US
David Wu - Austin TX, US
James F. Buller - Austin TX, US
Jingrong Zhou - Austin TX, US
Akif Sultan - Austin TX, US

Globalfoundries Inc. - Grand Cayman

G06F 17/50
H01L 21/8238

716 19, 716 21, 438199

The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.

7803670, Sep 28, 2010

Jul 20, 2006

11/458902

Ted R. White - Austin TX, US
Leo Mathew - Austin TX, US
Zhonghai Shi - Austin TX, US
Mariam G. Sadaka - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/00

438151, 438150, 438156, 438738, 257347, 257349, 257E3104, 257E2109, 257E21123, 257E2146

A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer () that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer () by a buried insulator layer (); forming an STI region () in the second semiconductor layer () and buried insulator layer (); exposing the first semiconductor layer () in a first area () of a STI region (); epitaxially growing a first epitaxial semiconductor layer () from the exposed first semiconductor layer (); and selectively etching the first epitaxial semiconductor layer () and the second semiconductor layer () to form CMOS FinFET channel regions (e. g. , ) and planar channel regions (e. g. , ) from the first epitaxial semiconductor layer () and the second semiconductor layer ().

7838345, Nov 23, 2010

May 2, 2006

11/416436

Zhonghai Shi - Austin TX, US
Héctor Sánchez - Cedar Park TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/00

438149, 257308, 257722, 257E21014, 257E21637, 257E21623

An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and contacting each of the first semiconductor fin and the second semiconductor fin along only a portion of length of each of the first semiconductor fin and the second semiconductor fin, respectively. In another aspect, a process for forming an electronic device can include forming a first semiconductor fin and a second semiconductor fin from a semiconductor layer, each of the first semiconductor fin and the second semiconductor fin spaced-apart from the other. The process can also include forming a bridge that contacts the first semiconductor fin and second semiconductor fin. The process can further include forming a conductive member, including a gate electrode, lying between the first semiconductor fin and second semiconductor fin.

8003466, Aug 23, 2011

Apr 8, 2008

12/099726

Zhonghai Shi - Austin TX, US
David Wu - Austin TX, US
Jingrong Zhou - Austin TX, US
Ruigang Li - Austin TX, US

Advanced Micro Devices, Inc. - Austin TX

H01L 21/336
H01L 21/00
H01L 21/84
H01L 21/338
H01L 21/8234
H01L 21/3205
H01L 21/4763
H01L 27/148
H01L 29/66
H01L 29/76
H01L 21/12
H01L 27/088

438283, 438149, 438157, 438176, 438197, 438585, 438587, 257241, 257287, 257288, 257347, 257401

A fabrication process for a FinFET device is provided. The process begins by providing a semiconductor wafer having a layer of conductive material such as silicon. A whole-field arrangement of fins is then formed from the layer of conductive material. The whole-field arrangement of fins includes a plurality of conductive fins having a uniform pitch and a uniform fin thickness. Next, a cut mask is formed over the whole-field arrangement of fins. The cut mask selectively masks sections of the whole-field arrangement of fins with a layout that defines features for a plurality of FinFET devices. The cut mask is used to remove a portion of the whole-field arrangement of fins, the portion being unprotected by the cut mask. The resulting fin structures are used to complete the fabrication of the FinFET devices.

8026142, Sep 27, 2011

May 8, 2009

12/463221

Zhonghai Shi - Austin TX, US
Jingrong Zhou - Austin TX, US

GLOBALFOUNDRIES Inc. - Grand Cayman

H01L 21/00

438279, 438286, 438302

A method of fabricating semiconductor devices begins by providing or fabricating a device structure that includes a semiconductor material and a plurality of gate structures formed overlying the semiconductor material. The method continues by creating light dose extension implants in the semiconductor material by bombarding the device structure with ions at a non-tilted angle relative to an exposed surface of the semiconductor material. During this step, the plurality of gate structures are used as a first implantation mask. The method continues by forming a patterned mask overlying the semiconductor material, the patterned mask being arranged to protect shared drain regions of the semiconductor material and to leave shared source regions of the semiconductor material substantially exposed. Thereafter, the method creates heavy dose extension implants and/or halo implants in the semiconductor material by bombarding the device structure with ions at a tilted angle relative to the exposed surface of the semiconductor material, and toward the plurality of gate structures. During this step, the plurality of gate structures and the patterned mask are used as a second implantation mask.

8134208, Mar 13, 2012

Sep 26, 2007

11/861928

Zhonghai Shi - Austin TX, US
David Wu - Austin TX, US
Mark Michael - Cedar Park TX, US
Donna Michael, legal representative - Cedar Park TX, US

GLOBALFOUNDRIES Inc. - Grand Cayman

H01L 27/12

257347, 438151, 257E27112

Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.

8329519, Dec 11, 2012

Nov 28, 2011

13/305449

Zhonghai Shi - Austin TX, US
David Wu - Austin TX, US
Mark Michael - Cedar Park TX, US
Donna Michael, legal representative - Cedar Park TX, US

GLOBALFOUNDRIES, Inc. - Grand Cayman

H01L 27/12

438151, 257347, 257E27112

Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.