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Zhimin Wan

from Irvine, CA
Age ~37
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Connected to:
Alexander S Wan, 57Alexis Wan, 42An C Wan, 38Brenda J Wan, 59Brenton O Wan, 70Carrie S Wan, 32Chelsea Wan, 30Chia Y Wan, 79Cho S Wan, 76Chooi P Wan, 58

Zhimin Wan Phones & Addresses

  • Irvine, CA
  • Chandler, AZ
  • Tempe, AZ
  • Doraville, GA

Work

Company: Microelectronics & emerging technologies thermal laboratory Aug 2011 Position: Graduate research assistant

Education

School / High School: Huazhong University of Science and Technology- Wuhan, CN May 2014 Specialities: M. S. in Mechanical Engineering

Resumes

Resumes

Zhimin Wan Photo 1

Postdoctoral Fellow

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Work:
Uga
Postdoctoral Fellow
Zhimin Wan Photo 2

Zhimin Wan Atlanta, GA

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Work:
Microelectronics & Emerging Technologies Thermal Laboratory

Aug 2011 to Sep 2014
Graduate Research Assistant
Georgia Tech

Jan 2014 to Apr 2014
Thermal Mechanical Analyst in a Course Project
Georgia Tech

May 2013 to Jul 2013
Thermal Packaging

Sep 2012 to Dec 2012
Thermal Analyst in a Course Project
National Laboratory for Optoelectronics
Wuhan, CN
Oct 2008 to Jun 2011
Graduate Research Assistant
Education:
Huazhong University of Science and Technology
Wuhan, CN
May 2014
M. S. in Mechanical Engineering
Georgia Institute of Technology
Atlanta, GA
Ph.D. in Mechanical Engineering

Publications

Us Patents

Tec-Embedded Dummy Die To Cool The Bottom Die Edge Hotspot

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US Patent:
20220199482, Jun 23, 2022
Filed:
Dec 22, 2020
Appl. No.:
17/131671
Inventors:
- Santa Clara CA, US
Zhimin WAN - Chandler AZ, US
Peng LI - Chandler AZ, US
Deepak GOYAL - Phoenix AZ, US
International Classification:
H01L 23/367
H01L 23/40
H01L 23/38
Abstract:
Embodiments disclosed herein include thermoelectric cooling (TEC) dies for multi-chip packages. In an embodiment, a TEC die comprises a glass substrate and an array of N-type semiconductor vias and P-type semiconductor vias through the glass substrate. In an embodiment, conductive traces are over the glass substrate, and individual ones of the conductive traces connect an individual one of the N-type semiconductor vias to an individual one of the P-type semiconductor vias.

Enhanced Base Die Heat Path Using Through-Silicon Vias

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US Patent:
20230128903, Apr 27, 2023
Filed:
Dec 23, 2022
Appl. No.:
18/088478
Inventors:
- Santa Clara CA, US
Kyle ARRINGTON - Gilbert AZ, US
Shankar DEVASENATHIPATHY - Tempe AZ, US
Aaron MCCANN - Queen Creek AZ, US
Nicholas NEAL - Gilbert AZ, US
Zhimin WAN - Chandler AZ, US
International Classification:
H01L 23/433
H01L 25/065
H01L 23/367
Abstract:
Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

Thermal Spreading Management Of 3D Stacked Integrated Circuits

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US Patent:
20210398966, Dec 23, 2021
Filed:
Aug 31, 2021
Appl. No.:
17/462794
Inventors:
- Santa Clara CA, US
Pooya Tadayon - Portland OR, US
Weihua Tang - Chandler AZ, US
Chandra M. Jha - Chandler AZ, US
Zhimin Wan - Chandler AZ, US
International Classification:
H01L 25/18
H01L 23/48
H01L 23/42
H01L 23/00
Abstract:
An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.

Enhanced Base Die Heat Path Using Through-Silicon Vias

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US Patent:
20210257277, Aug 19, 2021
Filed:
Feb 19, 2020
Appl. No.:
16/794789
Inventors:
- Santa Clara CA, US
Kyle ARRINGTON - Gilbert AZ, US
Shankar DEVASENATHIPATHY - Tempe AZ, US
Aaron MCCANN - Queen Creek AZ, US
Nicholas NEAL - Gilbert AZ, US
Zhimin WAN - Chandler AZ, US
International Classification:
H01L 23/433
H01L 23/367
H01L 25/065
Abstract:
Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

Device, System And Method For Providing Microchannels With Porous Sidewall Structures

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US Patent:
20200409398, Dec 31, 2020
Filed:
Jun 25, 2019
Appl. No.:
16/452280
Inventors:
- Santa Clara CA, US
Shankar Devasenathipathy - Tempe AZ, US
Zhimin Wan - Chandler AZ, US
Hardikkumar Prajapati - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G05D 23/185
H01L 23/373
H01L 23/473
Abstract:
Techniques and mechanisms for enabling a flow of fluid through microchannels of a fluid conduit, which is thermally coupled to cool integrated circuitry. In an embodiment, sidewall structures of the fluid conduit extend from a base structure to form at least in part microchannels, which extend along the base structure. The sidewall structures accommodate a flow of a coolant fluid through the fluid conduit, where the flow in turn facilitates conduction of heat, which has been transferred to the fluid conduit from the integrated circuitry. The sidewall structures comprise pores, which extend through a corresponding sidewall structure between two microchannel regions. In another embodiment, a sidewall structure provides a gradient of average porosity along one or more dimensions.

Deflected-Pillar Composite Compliant Elongated Micro-Structure Thermal Interface Materials

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US Patent:
20200411408, Dec 31, 2020
Filed:
Jun 27, 2019
Appl. No.:
16/454393
Inventors:
- Santa Clara CA, US
Pooya Tadayon - Hillsboro OR, US
Michael Rutigliano - Chandler AZ, US
Chandra M. Jha - Chandler AZ, US
Zhimin Wan - Chandler AZ, US
International Classification:
H01L 23/373
H01L 25/065
H01L 25/18
H01L 23/367
H01L 23/427
F28F 13/00
Abstract:
Disclosed embodiments include composite compliant pillars in a micro-structure array that extend at a non-orthogonal angle from a heat-sink base. The array is deployed against an integrated-circuit device package to deflect the composite compliant pillar array under conditions where heat-transfer performance is agnostic to dynamic non-planarity of the integrated-circuit device package.

Socket Loading Mechanism For Passive Or Active Socket And Package Cooling

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US Patent:
20200411410, Dec 31, 2020
Filed:
Jun 27, 2019
Appl. No.:
16/454343
Inventors:
- Santa Clara CA, US
Zhimin Wan - Chandler AZ, US
Chia-Pin Chiu - Tempe AZ, US
Shankar Devasenathipathy - Tempe AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/40
H01R 12/71
H01L 23/427
H01R 12/70
H01R 13/73
Abstract:
A microprocessor mounting apparatus comprising a microprocessor socket on a printed circuit board (PCB) and a bolster plate surrounding a perimeter of the microprocessor socket. The bolster plate has a first surface adjacent to the PCB, and a second surface opposite the first surface. A heat dissipation device is on the second surface of the bolster plate. The heat dissipation interface is thermally coupled to the microprocessor socket.

Thermal Spreading Management Of 3D Stacked Integrated Circuits

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US Patent:
20200388603, Dec 10, 2020
Filed:
Jun 6, 2019
Appl. No.:
16/433756
Inventors:
- Santa Clara CA, US
Pooya Tadayon - Hillsboro OR, US
Weihua Tang - Chandler AZ, US
Chandra M. Jha - Chandler AZ, US
Zhimin Wan - Chandler AZ, US
International Classification:
H01L 25/18
H01L 23/48
H01L 23/00
H01L 23/42
Abstract:
An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.
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Zhimin Wan from Irvine, CA, age ~37 Get Report