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Zhiyuan Yuan Wu

from Fremont, CA
Age ~61
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Also known as:
Zhi Yuan Wu, Zhi Y Wu, Zhi Yuan Zhu, Zhi Y Zhu, Zhiyuan Yuan Zhu, Zhi Ywu, N Wu
Related to:
Di Zhu, 34
Connected to:
Aihua Wu, 40Ailsa T Wu, 53Alice H Wu, 55Alix S Wu, 52Amie Wu, 39Angela Y Wu, 72Anqi Wu, 44Anqiang Wu, 48Banting H Wu, 63Baodong Wu, 62

Zhiyuan Wu Phones & Addresses

  • Fremont, CA
  • Union City, CA
  • San Jose, CA
  • Alameda, CA
  • Santa Fe, NM
  • 2060 Ojibwa Ct, Fremont, CA 94539 (510) 928-5356

Work

Position: Food Preparation and Serving Related Occupations

Education

Degree: High school graduate or higher

Public records

Vehicle Records

Zhiyuan Wu

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Address:
6631 Canterbury Ct, San Jose, CA 95129
VIN:
5FNYF18518B029947
Make:
HONDA
Model:
PILOT
Year:
2008

Business Records

Name / Title
Company / Classification
Phones & Addresses
Zhiyuan Wu
President
Hertz Communications, Inc
6631 Canterbury Ct, San Jose, CA 95129

Publications

Us Patents

Diffusion Regions Having Different Depths

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US Patent:
8299564, Oct 30, 2012
Filed:
Sep 14, 2009
Appl. No.:
12/559457
Inventors:
Yun Wu - San Jose CA, US
Bei Zhu - Los Gatos CA, US
Zhiyuan Wu - San Jose CA, US
Michael J. Hart - Palo Alto CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H01L 21/336
H01L 21/8234
US Classification:
257509, 257499, 257500, 257183, 257192, 257200, 257201, 438700, 438743
Abstract:
Formation of transistors, such as, e. g. , PMOS transistors, with diffusion regions having different depths for equalization of performance among transistors of an integrated circuit is described. Shallow-trench isolation structures are formed in a substrate formed at least in part of silicon for providing the transistors with at least substantially equivalent channel widths and lengths. A series of masks and etches is performed to form first recesses and second recesses defined in the silicon having different depths and respectively associated with first and second transistors. The second recesses are deeper than the first recesses. A silicon germanium film is formed in the first recesses and the second recesses. The silicon germanium film in the second recesses is thicker than the silicon germanium film in the first recesses, in order to increase performance of the second transistor so it is closer to the performance of the first transistor.

Method Of Product Performance Improvement By Selective Feature Sizing Of Semiconductor Devices

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US Patent:
8302064, Oct 30, 2012
Filed:
Mar 10, 2009
Appl. No.:
12/401450
Inventors:
Sharmin Sadoughi - Menlo Park CA, US
Prabhuram Gopalan - Milpitas CA, US
Michael J. Hart - Palo Alto CA, US
John Cooksey - Brentwood CA, US
Zhiyuan Wu - Sunnyvale CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 9/455
G06F 17/50
US Classification:
716133, 716119, 716132
Abstract:
Device features, such as gate lengths and channel widths, are selectively altered by first identifying those devices within a semiconductor die that exhibit physical attributes, e. g. , leakage current and threshold voltage magnitude, that are different than previously verified by a design/simulation tool used to design the devices. The identified, non-conforming devices are then further identified by the amount of deviation from the original design goal that is exhibited by each non-conforming device. The non-conforming devices are then mathematically categorized into bins, where each bin is tagged with a magnitude of deviation from a design goal. The mask layers defining the features of the non-conforming devices are then selectively modified by an amount that is commensurate with the tagged deviation. The selectively modified mask layers are then used to generate a new semiconductor die that exhibits improved performance.

Semiconductor Device And Method For Making The Same

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US Patent:
8329568, Dec 11, 2012
Filed:
May 3, 2010
Appl. No.:
12/772969
Inventors:
Myongseob Kim - Pleasanton CA, US
Ping-Chin Yeh - San Jose CA, US
Zhiyuan Wu - San Jose CA, US
John Cooksey - Brentwood CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H01L 21/425
US Classification:
438529, 257274, 257E21446, 257E29266
Abstract:
In one embodiment of the present invention, a field effect transistor device is provided. The field effect transistor device comprises an active area, including a first semiconductor material of a first conductivity type. A channel region is included within the active area. A gate region overlays the channel region, and the first source/drain region and the second source/drain region are embedded in the active area and spaced from each other by the channel region. The first source/drain region and the second source/drain region each include a second semiconductor material of a second conductivity type opposite of the first conductivity type. A well-tap region is embedded in the active area and spaced from the first source/drain region by the channel region and the second source/drain region. The well-tap region includes the second semiconductor material of the first conductivity type. The first source/drain region and the second source/drain region and the well-tap region are epitaxial deposits.

Integrated Circuit With Stress Inserts

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US Patent:
8350253, Jan 8, 2013
Filed:
Jan 29, 2010
Appl. No.:
12/697027
Inventors:
Bei Zhu - Los Gatos CA, US
Bang-Thu Nguyen - Santa Clara CA, US
Qi Lin - Cupertino CA, US
Zhiyuan Wu - San Jose CA, US
Ping-Chin Yeh - San Jose CA, US
Yun Wu - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H01L 29/06
US Classification:
257 19, 257E29193
Abstract:
An integrated circuit (“IC”) fabricated on a semiconductor substrate has an active gate structure formed over a channel region in the semiconductor substrate. A dummy gate structure is formed on a dielectric isolation structure. The dummy gate structure and the active gate structure have the same width. A sidewall spacer on the dummy gate structure overlies a semiconductor portion between a strain-inducing insert and the dielectric isolation structure.

Method And Apparatus For Improving A Circuit Layout Using A Hierarchical Layout Description

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US Patent:
7793238, Sep 7, 2010
Filed:
Mar 24, 2008
Appl. No.:
12/053874
Inventors:
Peter Rabkin - Cupertino CA, US
Zhiyuan Wu - Sunnyvale CA, US
Min-Hsing Peter Chen - Campbell CA, US
Jane W. Sowards - Fremont CA, US
Michael J. Hart - Palo Alto CA, US
Min-Fang Ho - Monte Sereno CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 2, 716 11, 716 19, 703 1
Abstract:
Various approaches for improving an integrated circuit layout. In one approach, a tree-type hierarchical layout representation of the circuit design is traversed. At each block visited during the traversing, a process determines whether there exists an improvement opportunity for each cell associated with the block. In response to determining that an improvement opportunity exists for a cell of a first block of the plurality of blocks, the process determines whether a modification to the cell satisfies one or more rules for every other block of the block type of the first block in the hierarchical representation. If the rules are satisfied, the modification is stored. Otherwise, the modification is discarded.

Ruthenium Liner And Cap For Back-End-Of-Line Applications

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US Patent:
20220344275, Oct 27, 2022
Filed:
Jul 6, 2022
Appl. No.:
17/858274
Inventors:
- Santa Clara CA, US
Feng Chen - San Jose CA, US
Tae Hong Ha - San Jose CA, US
Xianmin Tang - San Jose CA, US
Lu Chen - Cupertino CA, US
Zhiyuan Wu - San Jose CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 23/532
H01L 23/522
H01L 21/768
Abstract:
Electronic devices and methods of forming electronic devices using a ruthenium or doped ruthenium liner and cap layer are described. A liner with a ruthenium layer and a cobalt layer is formed on a barrier layer. A conductive fill forms a second conductive line in contact with the first conductive line.

Doped Selective Metal Caps To Improve Copper Electromigration With Ruthenium Liner

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US Patent:
20220336271, Oct 20, 2022
Filed:
Jun 23, 2022
Appl. No.:
17/848162
Inventors:
- Santa Clara CA, US
Zhiyuan WU - San Jose CA, US
International Classification:
H01L 21/768
H01L 21/285
H01L 23/532
Abstract:
Embodiments of the present disclosure are related to improved methods for forming an interconnect structure in a substrate. In one implementation, the method includes forming a barrier layer on exposed surfaces of a feature in a dielectric layer, forming a liner layer on the barrier layer, forming a seed layer on the liner layer, forming a metal fill on the seed layer by a metal fill process and overburdening the feature using an electroplating process, performing a planarization process to expose a top surface of the dielectric layer, and selectively forming a cobalt-aluminum alloy cap layer on the barrier layer, the liner layer, the seed layer, and the metal fill by exposing the substrate to a cobalt-containing precursor and an aluminum-containing precursor.

Method Of Forming A Metal Liner For Interconnect Structures

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US Patent:
20230072614, Mar 9, 2023
Filed:
Sep 3, 2021
Appl. No.:
17/466732
Inventors:
- Santa Clara CA, US
Zhiyuan Wu - San Jose CA, US
Feng Chen - San Jose CA, US
Carmen Leal Cervantes - Mountain View CA, US
Yong Jin Kim - Albany CA, US
Kevin Kashefi - San Ramon CA, US
Xianmin Tang - San Jose CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/768
Abstract:
Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.
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Zhiyuan Yuan Wu from Fremont, CA, age ~61 Get Report