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Zhenbin Ge

from San Jose, CA
Age ~46
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Also known as:
Ge Ge Zhenbin, Ge Fan Zhenbin, Zhenbin Zhenbin Ge
Phone and address:
2463 Ottawa Way, San Jose, CA 95130
Related to:
Weiqing Ge
Connected to:
Danny Ge, 60Edward G Ge, 83Guizhen Ge, 78Lina Ge, 46Nelson N Ge, 58Peinan Ge, 37Peter Z Ge, 31Ping Ge, 57Qian Z Ge, 34Siyu Ge, 47

Zhenbin Ge Phones & Addresses

  • 2463 Ottawa Way, San Jose, CA 95130
  • Santa Clara, CA
  • Sunnyvale, CA
  • Fremont, CA
  • Urbana, IL
  • Champaign, IL

Resumes

Resumes

Zhenbin Ge Photo 1

Technologist

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Applied Materials - United States since Dec 2011
Member of Technical Staff
Applied Materials - United States Aug 2007 - Dec 2011
Senior Process Engineer
Applied Materials - United States Jun 2006 - Aug 2007
Process Engineer
Education:
University of Illinois at Urbana-Champaign 2002 - 2006
Ph.D., Materials Science and Engineering Tsinghua University 2000 - 2002
M.S., Materials Science and Engineering Tsinghua University 1996 - 2000
B.S., Materials Science and Engineering
Skills:
Thin Films
Characterization
Cvd
Pvd
Semiconductors
Nanotechnology
Thin Film Characterization
Afm
Pecvd
Materials
Powder X Ray Diffraction
Atomic Layer Deposition
Plasma Physics
Metrology
Process Integration
Thermal
Sputtering
Etching
Program Management
Problem Solving
Vhf Plasma
Physical Vapor Deposition
Chemical Vapor Deposition
Thin Film Deposition
Magnetron Plasma
Engineering Statistics
Xrr/Xrf
Meta Pulse
Comsol Multiphysics Simulation
Interests:
Reading
Hiking
Pingpong
Tennis
Swimming
Languages:
English
Mandarin
Zhenbin Ge Photo 2

Zhenbin Ge

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Publications

Us Patents

Selective Etching Of Silicon Nitride

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US Patent:
8252696, Aug 28, 2012
Filed:
Oct 7, 2008
Appl. No.:
12/247059
Inventors:
Xinliang Lu - Fremont CA, US
Haichun Yang - Santa Clara CA, US
Zhenbin Ge - San Mateo CA, US
Nan Lu - San Jose CA, US
David T. Or - Santa Clara CA, US
Mei Chang - Saratoga CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/302
US Classification:
438744, 438714, 438723, 438738
Abstract:
Methods for etching dielectric layers comprising silicon and nitrogen are provided herein. In some embodiments, such methods may include providing a substrate having a dielectric layer comprising silicon and nitrogen disposed thereon, forming reactive species from a process gas comprising hydrogen (H) and nitrogen trifluoride (NF) using a remote plasma; and etching the dielectric layer using the reactive species. In some embodiments, an oxide layer is disposed adjacent to the dielectric layer. In some embodiments, the flow rate ratio of the process gas can be adjusted such that an etch selectivity of the dielectric layer to at least one of the oxide layer or the substrate is between about 0. 8 to about 4.

Method And Apparatus For Trench And Via Profile Modification

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US Patent:
8268684, Sep 18, 2012
Filed:
Aug 8, 2011
Appl. No.:
13/205379
Inventors:
Mei Chang - Saratoga CA, US
Xinliang Lu - Fremont CA, US
Zhenbin Ge - Santa Clara CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/00
US Classification:
438243, 438386, 438629, 438637
Abstract:
Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to methods and apparatus for profile modification prior to filling a structure, such as a trench or a via. One embodiment of the present invention comprises forming a sacrifice layer to pinch off a top opening of a structure by exposing the structure to an etchant. In one embodiment, the etchant is configured to remove the first material by reacting with the first material and generating a by-product, which forms the sacrifice layer.

Method And Apparatus For Trench And Via Profile Modification

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US Patent:
7994002, Aug 9, 2011
Filed:
Nov 18, 2009
Appl. No.:
12/620799
Inventors:
Mei Chang - Saratoga CA, US
Xinliang Lu - Fremont CA, US
Zhenbin Ge - Santa Clara CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/00
US Classification:
438243, 438386, 438629, 438637
Abstract:
Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to methods and apparatus for trench and via profile modification prior to filling the trench and via. One embodiment of the present invention comprises forming a sacrifice layer to pinch off a top opening of a trench structure by exposing the trench structure to an etchant. In one embodiment, the etchant is configured to remove the first material by reacting with the first material and generating a by-product, which forms the sacrifice layer.

Integration Sequences With Top Surface Profile Modification

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US Patent:
8043933, Oct 25, 2011
Filed:
Nov 18, 2009
Appl. No.:
12/620806
Inventors:
Xinliang Lu - Fremont CA, US
Zhenbin Ge - San Jose CA, US
Mei Chang - Saratoga CA, US
Hoiman Raymond Hung - Cupertino CA, US
Nitin Ingle - Santa Clara CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/76
US Classification:
438430, 438401, 438412, 438424, 438432, 438437, 257E21546
Abstract:
Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to apparatus and methods for forming shallow trench isolations having recesses with rounded bottoms. One embodiment of the present invention comprises forming a recess in a filled trench structure by removing a portion of a material from the filled trench structure and rounding bottom corners of the recess. Rounding bottom corners is performed by depositing a conformal layer of the same material filled in the trench structure over the substrate and removing the conformal layer of the material from sidewalls of the recess.

Methods Of Thin Film Process

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US Patent:
20080182382, Jul 31, 2008
Filed:
Nov 29, 2007
Appl. No.:
11/947674
Inventors:
Nitin K. Ingle - Santa Clara CA, US
Jing Tang - Santa Clara CA, US
Yi Zheng - San Jose CA, US
Zheng Yuan - Fremont CA, US
Zhenbin Ge - San Jose CA, US
Xinliang Lu - Fremont CA, US
Vikash Banthia - Mountain View CA, US
William H. McClintock - Los Altos CA, US
Mei Chang - Saratoga CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/762
US Classification:
438435, 257E21546
Abstract:
A method for forming a semiconductor structure includes forming a plurality of features across a surface of a substrate, with at least one space being between two adjacent features. A first dielectric layer is formed on the features and within the at least one space. A portion of the first dielectric layer interacts with a reactant derived from a first precursor and a second precursor to form a first solid product. The first solid product is decomposed to substantially remove the portion of the first dielectric layer. A second dielectric layer is formed to substantially fill the at least one space.

Process With Saturation At Low Etch Amount For High Contact Bottom Cleaning Efficiency For Chemical Dry Clean Process

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US Patent:
20090191703, Jul 30, 2009
Filed:
Jan 29, 2008
Appl. No.:
12/021844
Inventors:
Xinliang Lu - Fremont CA, US
Haichun Yang - Santa Clara CA, US
Zhenbin Ge - San Jose CA, US
Mei Chang - Saratoga CA, US
International Classification:
H01L 21/4763
H01L 21/302
US Classification:
438637, 438706, 257E21214, 257E21495
Abstract:
A method for removing oxides from the bottom surface of a contact hole is provided. The method provides efficient cleaning of the bottom surface without distortion of the contact hole upper and sidewall surfaces.

Nf3/H2 Remote Plasma Process With High Etch Selectivity Of Psg/Bpsg Over Thermal Oxide And Low Density Surface Defects

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US Patent:
20100099263, Apr 22, 2010
Filed:
Oct 20, 2008
Appl. No.:
12/254716
Inventors:
Xinliang Lu - Fremont CA, US
Haichun Yang - Santa Clara CA, US
Zhenbin Ge - Fremont CA, US
David T. Or - Santa Clara CA, US
Mei Chang - Saratoga CA, US
Assignee:
APPLIED MATERIALS, INC. - Santa Clara CA
International Classification:
H01L 21/34
H01L 21/465
H01L 21/428
US Classification:
438703, 438735, 438707, 257E21485, 257E21475, 257E2146
Abstract:
A method and apparatus for selectively etching doped semiconductor oxides faster than undoped oxides. The method comprises applying dissociative energy to a mixture of nitrogen trifluoride and hydrogen gas remotely, flowing the activated gas toward a processing chamber to allow time for charged species to be extinguished, and applying the activated gas to the substrate. Reducing the ratio of hydrogen to nitrogen trifluoride increases etch selectivity. A similar process may be used to smooth surface defects in a silicon surface.

High Pressure Rf-Dc Sputtering And Methods To Improve Film Uniformity And Step-Coverage Of This Process

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US Patent:
20100252417, Oct 7, 2010
Filed:
Apr 5, 2010
Appl. No.:
12/754473
Inventors:
Adolph Miller Allen - Oakland CA, US
Lara Hawrylchak - San Jose CA, US
Zhigang Xie - San Jose CA, US
Muhammad M. Rasheed - San Jose CA, US
Rongjun Wang - Dublin CA, US
Xianmin Tang - San Jose CA, US
Zhendong Liu - San Jose CA, US
Srinivas Gandikota - Santa Clara CA, US
Mei Chang - Saratoga CA, US
Michael S. Cox - San Jose CA, US
Donny Young - San Jose CA, US
Kirankumar Savandaiah - Bangalore, IN
Zhenbin Ge - San Jose CA, US
Assignee:
APPLIED MATERIALS, INC. - Santa Clara CA
International Classification:
C23C 14/34
US Classification:
20419212, 20429808
Abstract:
Embodiments of the invention generally provide a processing chamber used to perform a physical vapor deposition (PVD) process and methods of depositing multi-compositional films. The processing chamber may include: an improved RF feed configuration to reduce any standing wave effects; an improved magnetron design to enhance RF plasma uniformity, deposited film composition and thickness uniformity; an improved substrate biasing configuration to improve process control; and an improved process kit design to improve RF field uniformity near the critical surfaces of the substrate. The method includes forming a plasma in a processing region of a chamber using an RF supply coupled to a multi-compositional target, translating a magnetron relative to the multi-compositional target, wherein the magnetron is positioned in a first position relative to a center point of the multi-compositional target while the magnetron is translating and the plasma is formed, and depositing a multi-compositional film on a substrate in the chamber.
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Zhenbin Ge from San Jose, CA, age ~46 Get Report