Zhao Rongrong Wu

7283520, Oct 16, 2007

Apr 19, 2002

10/126466

Heng Liao - Belcarra, CA
Xiaofeng Wang - British Columbia, CA
Zhao Wu - San Jose CA, US

PMC-Sierra, Inc. - Burnaby

H04Q 11/00
H04L 12/28

370357, 370386, 370413

Multi-stage networks are used for data stream permutations involving merging and demultiplexing—providing arbitrary data unit time-space interchange that can be used to solve a range of problems particularly in the field of digital data communications, particularly in digital data communication involving advanced networks for exchanging data in packets, cells, or other data units.

7394828, Jul 1, 2008

Aug 30, 2002

10/233306

Zhao Wu - San Jose CA, US

PMC-Sierra, Inc. - Santa Clara CA

H04J 3/00
H04J 3/06

370476, 370509

A data format conversion method and apparatus are presented to convert time-slot interleaved SONET/SDH data to per time-slot data for virtual concatenation processing. The converter consists of an input buffer and a matrix transposer. The input buffer discards the overhead and fixed stuff bytes of each SPE that it receives, while the matrix transposer packs the N payload bytes into N-byte words with alignment to a start-of-frame indicator. Because each N-byte word is associated with a different time slot, the N-byte words form per time-slot data.

7415048, Aug 19, 2008

Aug 30, 2002

10/232961

Zhao Wu - San Jose CA, US

PMC-Sierra, Inc. - Santa Clara CA

H04J 3/16

370542, 370509, 370536

An alignment logic together with an MFI extractor are adapted to compensate for differential delays. The MFI extractor extracts the MFI disposed in the path overhead of each constituent time-slot. The alignment logic uses the extracted MFI to align corresponding data words (i. e. , data words that are transmitted during the same time period) at the receiving end of virtually concatenated channels and that occupy different time-slots of the same channel. To perform alignment, the alignment logic stores each data word in a RAM location that is defined by an associated MFI. The data words so stored are aligned when read sequentially from their stored locations. The synchronization logic in the alignment logic synchronizes all the constituent time-slots.

7724781, May 25, 2010

Aug 30, 2002

10/232962

Zhao Wu - San Jose CA, US
Heng Liao - Belcarra, CA

PMC-Sierra, Inc. - Santa Clara CA

H04J 3/06
H04J 3/16

370510, 370542, 710 53

A receive virtual concatenation processor (processor) is adapted to receive time-slot interleaved data carried over SONET/SDH frames. The processor first generates per time-slot data and subsequently generates per channel data. The processor supports virtual concatenation, contiguous concatenation as well as mixed concatenation in which some channels are contiguously concatenated and others are virtually concatenated. The processor supports virtual concatenation at both STS-1 and STS-3c granularities and with arbitrary differential delay among constituent time-slots. The processor supports contiguous concatenation with any multiple of STS-3c granularity. The processor is highly scalable to support multiple channels and different frame sizes such as STS-12, STS-48, STS-192, etc.

20010046233, Nov 29, 2001

May 25, 2001

09/865976

Zhao Wu - San Jose CA, US

H04L012/28
H04L012/56
H04J003/16

370/395000, 370/466000

According to the invention, an ATM cell format extender or converter includes a memory and write and read state machines which are symmetric as facilitated by the memory and signals applied to the state machines. The write state machine receives information defining the format of an incoming ATM cell, and, in response, sequences through a first selected state sequence. While in each state of the selected sequence, the write state machine decodes a particular address in memory in which an associated byte of the incoming cell is stored. The read state machine receives information defining the format of an outgoing ATM cell, and, in response, sequences through a second selected state sequence. While in each state of the selected sequence, the read state machine decodes a particular address in the memory from which an associated byte of the outgoing cell is retrieved, thereby to construct the outgoing cell. The read and write state machines are preferably identical. Each of the write and read state machines in a specific embodiment is a 4-bit state machine with 16 Gray encoded states.

20030043851, Mar 6, 2003

Aug 30, 2001

09/943886

Zhao Wu - San Jose CA, US
Heng Liao - Belcarra, CA

PMC-Sierra, Inc. - Burnaby BC

H04J003/07

370/476000, 370/506000, 370/539000

A transmit virtual concatenation processor for multiplexing channelized data onto a SONET/SDH frame is disclosed. The processor is scalable and is able to handle mapping a number of data channels to a number of different frame sizes including STS-STS-STS-and STS-The processor supports virtual concatenation with arbitrary channel mapping at both STS-and STS-granularities. The processor also supports contiguous concatenation with STS-STS-STS-STS-etc. capacities (i.e., STS-Nc where N is a multiple of 3). In addition, the processor supports mixed concatenation where some channels are using contiguous concatenation and some other channels are using STS--Xv virtual concatenation. Alternatively, the processor is able to support any virtual concatenation, any contiguous concatenation and any mixed concatenation. The processor terminates the HHand Hbytes in the line overhead of a SONET/SDH frame and inserts the multi-frame indicator and sequence number in the Hbyte of the path overhead.