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Zhao Wu Phones & Addresses

  • Deerfield, IL
  • Chicago, IL
  • Austin, TX
  • 151 Hackamore Cmn, Fremont, CA 94539 (510) 438-0106
  • Alameda, CA
  • San Jose, CA
  • Princeton, NJ

Professional Records

Medicine Doctors

Zhao Wu Photo 1

Zhao Wu

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Specialties:
Pathology
Blood Banking & Transfusion Medicine
Hematology

Business Records

Name / Title
Company / Classification
Phones & Addresses
Mr. Zhao Wu
Owner
Eng's Asian Cuisine
Eng's Orient Express
Restaurants
7300 N Western Ave, Chicago, IL 60645
(773) 465-2476
Zhao Qi Wu
Voidthebrand LLC
Online Fashion Retailer
1000 Franklin St, San Francisco, CA 94109
888 Ofarrell St, San Francisco, CA 94109
643 Msn St, San Francisco, CA 94105
Mr. Zhao Wu
Owner
Eng's Asian Cuisine
Eng's Orient Express
Restaurants
7300 N Western Ave, Chicago, IL 60645
(773) 465-2476

Publications

Us Patents

Data Stream Permutation Applicable To Large Dimensions

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US Patent:
7283520, Oct 16, 2007
Filed:
Apr 19, 2002
Appl. No.:
10/126466
Inventors:
Heng Liao - Belcarra,
Xiaofeng Wang - British Columbia,
Zhao Wu - San Jose CA,
Assignee:
PMC-Sierra, Inc. - Burnaby
International Classification:
H04Q 11/00
H04L 12/28
US Classification:
370357, 370386, 370413
Abstract:
Multi-stage networks are used for data stream permutations involving merging and demultiplexing—providing arbitrary data unit time-space interchange that can be used to solve a range of problems particularly in the field of digital data communications, particularly in digital data communication involving advanced networks for exchanging data in packets, cells, or other data units.

Data Format Conversion For Virtual Concatenation Processing

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US Patent:
7394828, Jul 1, 2008
Filed:
Aug 30, 2002
Appl. No.:
10/233306
Inventors:
Zhao Wu - San Jose CA,
Assignee:
PMC-Sierra, Inc. - Santa Clara CA
International Classification:
H04J 3/00
H04J 3/06
US Classification:
370476, 370509
Abstract:
A data format conversion method and apparatus are presented to convert time-slot interleaved SONET/SDH data to per time-slot data for virtual concatenation processing. The converter consists of an input buffer and a matrix transposer. The input buffer discards the overhead and fixed stuff bytes of each SPE that it receives, while the matrix transposer packs the N payload bytes into N-byte words with alignment to a start-of-frame indicator. Because each N-byte word is associated with a different time slot, the N-byte words form per time-slot data.

Differential Delay Compensation

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US Patent:
7415048, Aug 19, 2008
Filed:
Aug 30, 2002
Appl. No.:
10/232961
Inventors:
Zhao Wu - San Jose CA,
Assignee:
PMC-Sierra, Inc. - Santa Clara CA
International Classification:
H04J 3/16
US Classification:
370542, 370509, 370536
Abstract:
An alignment logic together with an MFI extractor are adapted to compensate for differential delays. The MFI extractor extracts the MFI disposed in the path overhead of each constituent time-slot. The alignment logic uses the extracted MFI to align corresponding data words (i. e. , data words that are transmitted during the same time period) at the receiving end of virtually concatenated channels and that occupy different time-slots of the same channel. To perform alignment, the alignment logic stores each data word in a RAM location that is defined by an associated MFI. The data words so stored are aligned when read sequentially from their stored locations. The synchronization logic in the alignment logic synchronizes all the constituent time-slots.

Receive Virtual Concatenation Processor

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US Patent:
7724781, May 25, 2010
Filed:
Aug 30, 2002
Appl. No.:
10/232962
Inventors:
Zhao Wu - San Jose CA,
Heng Liao - Belcarra,
Assignee:
PMC-Sierra, Inc. - Santa Clara CA
International Classification:
H04J 3/06
H04J 3/16
US Classification:
370510, 370542, 710 53
Abstract:
A receive virtual concatenation processor (processor) is adapted to receive time-slot interleaved data carried over SONET/SDH frames. The processor first generates per time-slot data and subsequently generates per channel data. The processor supports virtual concatenation, contiguous concatenation as well as mixed concatenation in which some channels are contiguously concatenated and others are virtually concatenated. The processor supports virtual concatenation at both STS-1 and STS-3c granularities and with arbitrary differential delay among constituent time-slots. The processor supports contiguous concatenation with any multiple of STS-3c granularity. The processor is highly scalable to support multiple channels and different frame sizes such as STS-12, STS-48, STS-192, etc.

Symmetric Universal Format Conversion Mechanism With Gray Code

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US Patent:
20010046233, Nov 29, 2001
Filed:
May 25, 2001
Appl. No.:
09/865976
Inventors:
Zhao Wu - San Jose CA,
International Classification:
H04L012/28
H04L012/56
H04J003/16
US Classification:
370/395000, 370/466000
Abstract:
According to the invention, an ATM cell format extender or converter includes a memory and write and read state machines which are symmetric as facilitated by the memory and signals applied to the state machines. The write state machine receives information defining the format of an incoming ATM cell, and, in response, sequences through a first selected state sequence. While in each state of the selected sequence, the write state machine decodes a particular address in memory in which an associated byte of the incoming cell is stored. The read state machine receives information defining the format of an outgoing ATM cell, and, in response, sequences through a second selected state sequence. While in each state of the selected sequence, the read state machine decodes a particular address in the memory from which an associated byte of the outgoing cell is retrieved, thereby to construct the outgoing cell. The read and write state machines are preferably identical. Each of the write and read state machines in a specific embodiment is a 4-bit state machine with 16 Gray encoded states.

Transmit Virtual Concatenation Processor

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US Patent:
20030043851, Mar 6, 2003
Filed:
Aug 30, 2001
Appl. No.:
09/943886
Inventors:
Zhao Wu - San Jose CA,
Heng Liao - Belcarra,
Assignee:
PMC-Sierra, Inc. - Burnaby BC
International Classification:
H04J003/07
US Classification:
370/476000, 370/506000, 370/539000
Abstract:
A transmit virtual concatenation processor for multiplexing channelized data onto a SONET/SDH frame is disclosed. The processor is scalable and is able to handle mapping a number of data channels to a number of different frame sizes including STS-STS-STS-and STS-The processor supports virtual concatenation with arbitrary channel mapping at both STS-and STS-granularities. The processor also supports contiguous concatenation with STS-STS-STS-STS-etc. capacities (i.e., STS-Nc where N is a multiple of 3). In addition, the processor supports mixed concatenation where some channels are using contiguous concatenation and some other channels are using STS--Xv virtual concatenation. Alternatively, the processor is able to support any virtual concatenation, any contiguous concatenation and any mixed concatenation. The processor terminates the HHand Hbytes in the line overhead of a SONET/SDH frame and inserts the multi-frame indicator and sequence number in the Hbyte of the path overhead.
Zhao Wu from Deerfield, IL, age ~48 Get Report