Zailong Z Zhuang

7791523, Sep 7, 2010

Oct 28, 2008

12/259344

Zailong Zhuang - Scarborough ME, US

Agere Systems, Inc. - Allentown PA

H03M 1/12

341156, 341155, 341160, 341169, 341164

A two-step ADC is provided that achieves significant improvements in the settling time window available for CDAC conversion, FADC sub-ranging and FADC conversion without increasing the amount of chip area or power that are consumed by the ADC. The ADC uses interleaved sampler/buffer circuits to sample the incoming analog signal on different phases of the clock signal. MUXes provide the samples obtained by the sampler/buffer circuits to the CADC and FADC circuits in ping pong fashion in such a way that the CADC and FADC circuits are converting during every clock period. In addition, these improvements are achieved without increasing the number of potential sources of bit decision mismatches in the two-step sub-ranging ADC.

20060245531, Nov 2, 2006

Apr 27, 2005

11/115671

Robert Leonowich - Fleetwood PA, US
Zailong Zhuang - Whitehall PA, US

H03D 3/24

375376000

A signal generator, such as a fractional-N PLL, has, in its feedback signal path, a divider, a phase circuit, and a fractional accumulator that generates control signals for the divider and the phase circuit. The divider control signal controls the divisor value applied by the divider. In one embodiment, a phase selector selects, based on the phase-circuit control signal, one of a plurality of phase-shifted output signals generated by the PLL's main signal path (e.g., by a multi-phase VCO) and the divider generates the feedback signal for the PLL from the selected signal. In another embodiment, the divider generates a divided signal from one of the phase-shifted output signals, and a phase mixer generates, from the divided signal, a plurality of phase-shifted divided signals and selects, based on the phase-circuit signal, one of the phase-shifted divided signals as the PLL's feedback signal.