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Yutao M Ma

from San Jose, CA
Age ~50
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Also known as:
Yutao Y Ma, Yuntao Ma, Ma Yutao
Phone and address:
1044 Liebelt Ct, San Jose, CA 95126
Related to:
Han R Ma, 64Rei Han ReiSha Ma, 39Litsing Ma, 67Amy C Ma, 77Ma HenrieLeejoan Ma Joan, 51Hen Rei Ma, 78
Connected to:
Ah N Ma, 70Aileen B Ma, 51Akana K Ma, 68Alex B Ma, 49Alexandra Ma, 33Allan Ma, 38Anni Ma, 39Annie Ma, 49Athena Ma, 30Ayan S Ma, 38

Yutao Ma Phones & Addresses

  • 1044 Liebelt Ct, San Jose, CA 95126
  • Las Vegas, NV
  • Pahrump, NV
  • 2952 Midhurst Way, San Jose, CA 95135 (408) 582-3625

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Resumes

Resumes

Yutao Ma Photo 1

Vice President Of R And D

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Location:
San Jose, CA
Industry:
Computer Software
Work:
Proplus Design Solutions, Inc.
Vice President of R and D
Proplus Design Solutions, Inc. Jan 2007 - Jun 2012
Architect and Director
Cadence Design Systems 2003 - 2007
Senior Member of Consulting Staff
Celestry Design Technologies Sep 2001 - Dec 2002
Software Engineer
Education:
Tsinghua University 1991 - 2001
Doctorates, Doctor of Philosophy
Skills:
Eda
Algorithms
C
Verilog
Soc
Software Development
Simulations
Linux
Semiconductors
C++
Software Engineering
Perl
Debugging
Matlab
Cmos
Asic
Ic
Object Oriented Design
Software Architectural Design
Product Management
Integrated Circuits
Management
Python
Jira
Languages:
English
Mandarin
Yutao Ma Photo 2

Yutao Ma

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Publications

Us Patents

Post Cu Cmp Polishing For Reduced Defects

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US Patent:
6436302, Aug 20, 2002
Filed:
Jan 27, 2000
Appl. No.:
09/492267
Inventors:
Fred C. Redeker - Fremont CA
Rajeev Bajaj - Fremont CA
Yutao Ma - Sunnyvale CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21463
US Classification:
216 38, 216 52, 216 53, 134 3, 134 7, 252 791, 438693, 510175
Abstract:
Cu metallization is treated to reduce defects and effect passivation, and to reduce leakage between lines, by removing surface defects subsequent to CMP and barrier layer removal. Embodiments include the sequential steps of: CMP and barrier layer removal; buffing with a solution comprising citric acid, ammonium hydroxide and deionized water to remove copper oxide; rinsing with deionized water or an inhibitor solution, e. g. , benzotriazole or 5-methyl triazole in deionized water; buffing with an abrasive slurry; and rinsing with deionized water or an inhibitor solution.

Method To Reduce Polish Initiation Time In A Polish Process

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US Patent:
6436832, Aug 20, 2002
Filed:
May 23, 2000
Appl. No.:
09/578157
Inventors:
Yutao Ma - Sunnyvale CA
Juilung Li - San Jose CA
Fred C. Redeker - Fremont CA
Rajeev Bajaj - Fremont CA
Assignee:
Applied Materials, Inc - Santa Clara CA
International Classification:
H01L 2100
US Classification:
438692, 134 2, 134 26, 216 38, 216 88, 216100, 438745, 438754
Abstract:
High through-put CMP is achieved by the application of a cleaning composition on to an exposed surface of a metal layer prior to polishing the bulk metal layer. Embodiments of the present invention include applying an aqueous composition containing citric acid and ammonium hydroxide in deionized water to remove a native oxide film that forms on a copper containing layer and then polishing the copper containing layer to substantially planarize the metal layer.

Method And Apparatus For Hard Pad Polishing

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US Patent:
6620027, Sep 16, 2003
Filed:
Jan 9, 2002
Appl. No.:
10/044379
Inventors:
Ajoy Zutshi - Fremont CA
Rajeev Bajaj - Fremont CA
Fred C. Redeker - Fremont CA
Yutao Ma - Fremont CA
Kapila Wijekoon - Palto Alto CA
Assignee:
Applied Materials Inc. - Santa Clara CA
International Classification:
B24B 5100
US Classification:
451 5, 451 57, 451 37
Abstract:
Methods and apparatus for planarizing a substrate surface having copper containing materials thereon is provided. In one aspect, the invention provides a system for processing substrates comprising a first platen adapted for polishing a substrate with a hard polishing pad disposed on the first platen, a second platen adapted for polishing a substrate with a hard polishing pad disposed on the second platen, and a third platen adapted for polishing a substrate with a hard polishing pad disposed on the third platen. In another aspect, the invention provides a method for planarizing a substrate surface by the system described above including substantially removing bulk copper containing materials on the first platen, removing residual copper containing materials on the second platen, and then removing a barrier layer on the third platen. A computer readable program may also be provided for performing the methods described herein.

Model Stamping Matrix Check Technique In Circuit Simulator

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US Patent:
7299428, Nov 20, 2007
Filed:
Feb 6, 2004
Appl. No.:
10/773541
Inventors:
Yutao Ma - San Jose CA, US
Bruce McGaughy - Fremont CA, US
Zhihong Liu - Cupertino CA, US
Assignee:
Cadence Design Systems, Inc - San Jose CA
International Classification:
G06F 177/50
US Classification:
716 4, 716 5
Abstract:
The present invention includes a method for detecting model stamping errors during circuit simulation without the need for golden data. The method checks for model stamping errors by determining whether entries in model stamping matrices interrelate according to a plurality of preset rules before circuit equations are solved.

Circuit Simulation With Decoupled Self-Heating Analysis

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US Patent:
7606693, Oct 20, 2009
Filed:
Sep 12, 2005
Appl. No.:
11/224249
Inventors:
Min-Che Jeng - Cupertino CA, US
Yutao Ma - San Jose CA, US
Zhihong Liu - Cupertino CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
703 14
Abstract:
A solution of a first set of equations of the time-varying electrical response of a circuit is determined between pairs of adjacent time points tand tbased on predicted electrical responses of the devices at time point tand as a function of the initial temperatures of the circuit devices at time point t. A solution of a second set of equations of the time-varying temperature responses of devices of the circuit is determined (1) after each iteration of the first set of equations and as a function thereof or (2) at each time point tand as a function of the solution of the first set of equations at the time point to determine the corresponding temperature response of the circuit. The solutions of the first and second sets of equations at one or more of the points in time are displayed.

Pad Conditioner

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US Patent:
7815495, Oct 19, 2010
Filed:
Apr 11, 2007
Appl. No.:
11/734063
Inventors:
Kun Xu - Fremont CA, US
Jimin Zhang - San Jose CA, US
James C. Wang - Saratoga CA, US
Thomas H. Osterheld - Mountain View CA, US
Yutao Ma - Fremont CA, US
Steven M. Zuniga - Soquel CA, US
Jin Yi - Sunnyvale CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
B24B 53/12
US Classification:
451443, 451444
Abstract:
A pad conditioner is provided for conditioning a polishing pad in chemical mechanical planarization (CMP). The pad conditioner comprises a plastic abrasive portion having a first hardness and optionally a brush portion having a second hardness less than the first hardness. The plastic abrasive portion comprises a base plate and a plurality of plastic nodules formed on a surface of the base plate, each of the plastic nodules having a planar top surface, wherein the planar top surface is positioned to substantially contact a polishing pad. The brush portion may be positioned adjacent to the plastic abrasive portion, the brush portion having a plurality of brush elements positioned to substantially contact the pad.

Method And System For Simulating Dynamic Behavior Of A Transistor

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US Patent:
7933747, Apr 26, 2011
Filed:
Nov 6, 2007
Appl. No.:
11/935969
Inventors:
Yutao Ma - San Jose CA, US
Bruce W. McGaughy - Fremont CA, US
Lifeng Wu - Fremont CA, US
Zhihong Liu - Cupertino CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/10
US Classification:
703 2, 703 13, 703 14, 703 15, 703 16, 703 17, 703 19, 716100, 716101, 716132, 716134, 716136
Abstract:
Method and system are disclosed for modeling dynamic behavior of a transistor. The method includes representing static behavior of a transistor using a lookup table, selecting an instance of the transistor from the lookup table for modeling dynamic behavior of the transistor, computing a previous state of the instance using a non-quasi static analytical model, computing a variation in channel charge of the instance according to a rate of change in time, computing a current state of the instance using the previous state and the variation in channel charge, computing a modified terminal voltage that includes a dynamic voltage across a parasitic resistance at the terminal of the transistor according to the current state and previous state of the instance, and storing the modified terminal voltage in a memory device for modeling dynamic behavior of the transistor at the current state.

Model Implementation On Gpu

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US Patent:
7979814, Jul 12, 2011
Filed:
Mar 12, 2008
Appl. No.:
12/047222
Inventors:
Yutao Ma - San Jose CA, US
Yi Xu - Cupertino CA, US
Assignee:
ProPlus Design Solutions, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716100
Abstract:
Model evaluation and circuit simulation/verification is performed in a graphical processing unit (GPU). A multitude of first texture data corresponding to size parameters of devices are stored. A multitude of second texture data corresponding to instance parameters of the devices are stored. A multitude of third texture data corresponding to models of the devices are stored. A multitude of fourth texture data corresponding to terminal voltages received by the device are stored. A multitude of links linking each device instance to an associated device model, size parameters and instance parameters are stored. A quad having a size defined by the multitude of links is drawn by the quad in the GPU. Each thread in the quad is assigned to a different one of the multitude of links. The computations are carried out in each thread using the linked data to perform the model evaluation.
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Yutao M Ma from San Jose, CA, age ~50 Get Report