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Youssef M Barakat

from Redmond, WA
Age ~46
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Also known as:
Barakat Youssef
Related to:
Marilyn YassaMarilyn S Yassa, 41
Connected to:
Ahmed Barakat, 56Andrew L Barakat, 32Ayman Barakat, 125Babak A Barakat, 52Dema E Barakat, 49Ebrahim Barakat, 49Fouad Barakat, 38Hatem L Barakat, 55Imad M Barakat, 68Jamil H Barakat, 38

Youssef Barakat Phones & Addresses

  • Redmond, WA
  • Bothell, WA
  • 538 Central Way, Kirkland, WA 98033 (425) 576-1905
  • Kiona, WA

Resumes

Resumes

Youssef Barakat Photo 1

Ibm Watson And Cloud Platform Technical

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Location:
Redmond, WA
Industry:
Information Technology And Services
Work:
Ibm
Ibm Watson and Cloud Platform Technical Sales and Technical Csm For Mea
Ibm Jul 2017 - Jan 2018
Ibm Cloud Infrastructure Technical Sales For Middle East and Africa
Ibm 2015 - Jan 2018
Ibm Mea, Cloud Solution Representative For North West Africa
Aldayra.com Aug 2014 - Sep 2014
It Intern
Cib Egypt Jul 2014 - Jul 2014
It Intern
Education:
College De La Sainte Famille 1997 - 2011
The German University In Cairo
Skills:
Digital Seller
Cloud Computing
Softlayer Iaas
Bluemix Paas
Java Programming
Web Development Ruby on Rails
Android Application Beginner
Research Skills
Leadership Skills
Self Motivated
Team Player
Fast Learner
Problem Solving
Sales
Microsoft Office
Business Analysis
Business Intelligence
Team Leadership
Program Management
Java
Leadership
Powerpoint
Requirements Analysis
Project Management
Integration
Linux
Interests:
Kick Boxing
Football
Boxing
Workout
Photography
Fitness
Sports
Music
Squash
Swimming
Movies
Languages:
English
Arabic
French
German
Certifications:
Softlayer Seller
Softlayer Solution Design
Ibm Global Sales School
Certificate In Professional Digital Selling
Vmware Sales Professional
Vmware Technical Sales Professional
Ibm Bluemix Practitioner Essentials Badge
Softlayer, An Ibm Company
Ibm
Digital Marketing Institute, License Accredible-10214699
Vmware
License Accredible-10214699
Youssef Barakat Photo 2

Engineering Manager

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Location:
Seattle, WA
Industry:
Internet
Work:
Google
Engineering Manager
Microsoft May 2016 - Nov 2018
Principal Group Engineering Manager
Microsoft Sep 2008 - Aug 2014
Principal Engineering Manager
Microsoft Mar 2007 - Sep 2008
Senior Software Design Engineer
Microsoft Nov 2002 - Mar 2007
Software Design Engineer Ii
Education:
University of Toronto - University of St. Michael's College 1996 - 2000
Bachelors, Bachelor of Science, Software Engineering
Skills:
Software Design
Kernel
Software Engineering
Device Drivers
C
Software Development
Arm
Debugging
Operating Systems
X86
Software Project Management
Soc
C++
Architecture
Testing
Multithreading
Team Management
Windows
Win32 Api
Languages:
Arabic
Youssef Barakat Photo 3

Youssef Barakat

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Location:
United States

Publications

Wikipedia References

Youssef Barakat Photo 4

Youssef Barakat

Us Patents

Rebootless Display Driver Upgrades

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US Patent:
8302089, Oct 30, 2012
Filed:
Sep 1, 2011
Appl. No.:
13/224179
Inventors:
Marcus J. Andrews - Bellevue WA, US
Max A. McMullen - Redmond WA, US
Sameer A. Nene - Redmond WA, US
Youssef M. Barakat - Bothell WA, US
Ameet A. Chitre - Duvall WA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06F 9/445
US Classification:
717171, 717176
Abstract:
Systems and methods for rebootless updating of a IHV display driver are disclosed. According to such a method, first, the operating system stops the driver from running Second, the system switches over to an interim or temporary display driver, which be a default driver provided with the operating system. Third, the new hardware-specific driver is started. Thus, a hardware-specific display driver may be updated without rebooting.

Rebootless Display Driver Upgrades

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US Patent:
20070101343, May 3, 2007
Filed:
Oct 31, 2005
Appl. No.:
11/263765
Inventors:
Marcus Andrews - Bellevue WA, US
Max McMullen - Redmond WA, US
Sameer Nene - Redmond WA, US
Youssef Barakat - Bothell WA, US
Ameet Chitre - Duvall WA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06F 9/46
US Classification:
719321000
Abstract:
Systems and methods for rebootless updating of a IHV display driver are disclosed. According to such a method, first, the operating system stops the driver from running. Second, the system switches over to an interim or temporary display driver, which be a default driver provided with the operating system. Third, the new hardware-specific driver is started. Thus, a hardware-specific display driver may be updated without rebooting.

Memory Ordering Annotations For Binary Emulation

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US Patent:
20210089282, Mar 25, 2021
Filed:
Dec 3, 2020
Appl. No.:
17/111340
Inventors:
- Redmond WA, US
Ten TZEN - Sammamish WA, US
Christopher Martin MCKINSEY - Sammamish WA, US
YongKang ZHU - Redmond WA, US
Terry MAHAFFEY - Apex NC, US
Pedro Miguel Sequeira de Justo TEIXEIRA - Kirkland WA, US
Arun Upadhyaya KISHAN - Kirkland WA, US
Youssef M. BARAKAT - Redmond WA, US
International Classification:
G06F 8/41
G06F 9/30
Abstract:
During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint. If so, the emulator emits machine code instruction(s) in the second ISA that perform the memory operation using a memory barrier.

Lock Free Distributed Transaction Coordinator For In-Memory Database Participants

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US Patent:
20200125654, Apr 23, 2020
Filed:
Oct 23, 2018
Appl. No.:
16/168637
Inventors:
- Redmond WA, US
Youssef M. Barakat - Redmond WA, US
Shirish Gajera - Sunnyvale CA, US
Karthick Krishnamoorthy - Sammamish WA, US
International Classification:
G06F 17/30
Abstract:
Methods, systems, apparatuses, and computer program products are provided for coordinating a distributed database transaction. A transaction driver, such as a client machine, may initiate a distributed transaction. The transaction driver may transmit to a transaction coordinator a driver report that includes identifying information related to the distributed transaction, including an identification of participants involved in the transaction. The coordinator may determine whether participant reports, which include a status of the portion of the distributed database transaction of a particular participant, are received from each of the participants. Participant reports may also identify participants that are descendants of the reporting participant. The transaction coordinator may store, in a table, information to track the progress of the distributed transaction. Using the table, an outcome of the distributed transaction may be determined and transmitted to one or more of the involved participants.

Memory Ordering Annotations For Binary Emulation

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US Patent:
20200110587, Apr 9, 2020
Filed:
Oct 4, 2018
Appl. No.:
16/152177
Inventors:
- Redmond WA, US
Ten TZEN - Sammamish WA, US
Christopher Martin MCKINSEY - Sammamish WA, US
YongKang ZHU - Redmond WA, US
Terry MAHAFFEY - Apex NC, US
Pedro Miguel Sequeira de Justo TEIXEIRA - Kirkland WA, US
Arun Upadhyaya KISHAN - Kirkland WA, US
Youssef M. BARAKAT - Redmond WA, US
International Classification:
G06F 8/41
G06F 9/30
Abstract:
During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint. If so, the emulator emits machine code instruction(s) in the second ISA that perform the memory operation using a memory barrier.

Tracking Work Between System Entities

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US Patent:
20180032378, Feb 1, 2018
Filed:
Jul 28, 2016
Appl. No.:
15/221953
Inventors:
- Redmond WA, US
Youssef Barakat - Bothell WA, US
Yevgeniy M. Bak - Redmond WA, US
Mehmet lyigun - Kirkland WA, US
Pedro Miguel Sequeira de Justo Teixeira - Kirkland WA, US
International Classification:
G06F 9/50
G06F 9/48
G06F 21/44
Abstract:
A computing system includes one or more processors and a storage device that stores computer executable instructions that can be executed by the processors to cause the computing system to perform the following. The system generates a work tracking information ticket for a first system entity. The system assigns the work tracking information ticket to the first system entity. The system passes the work tracking information ticket to one or more second system entities. The system validates the work tracking information ticket. The validated work tracking information ticket informs that the one or more second system entities are performing work on behalf of the first system entity.

Translating Atomic Read-Modify-Write Accesses

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US Patent:
20170235557, Aug 17, 2017
Filed:
Feb 16, 2016
Appl. No.:
15/044707
Inventors:
- Redmond WA, US
Youssef Barakat - Bothell WA, US
Arun Kishan - Kirkland WA, US
Assignee:
Microsoft Technology Licensing, LLC. - Redmond WA
International Classification:
G06F 9/45
Abstract:
Various systems and methods for translating atomic read-modify-write accesses are described herein. In one example, a method includes determining that a machine instruction of a first language specifies an atomic read-modify-write access. The method includes generating machine instructions of the second language to perform an atomic access for the address if the address is aligned. The method includes generating machine instructions of a second language to acquire a global lock if the address is unaligned. Additionally, the method includes generating machine instructions of the second language to perform a non-atomic access for the address if the address is unaligned. Also, the method includes generating machine instructions of the second language to release the global lock if the address is unaligned.

Operating System-Managed Interrupt Steering In Multiprocessor Systems

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US Patent:
20160357689, Dec 8, 2016
Filed:
Aug 19, 2016
Appl. No.:
15/241104
Inventors:
- Redmond WA, US
Minsang Kim - Redmond WA, US
Jason Wohlgemuth - Duvall WA, US
Tristan Brown - Bellevue WA, US
Youssef Barakat - Bothell WA, US
Omid Fatemieh - Redmond WA, US
International Classification:
G06F 13/24
Abstract:
An operating system includes an interrupt router that dynamically steers each interrupt to one or more processors within set of processors based on overall load information from the set of processors. An interrupt source is assigned to a processor based on the load imposed by the interrupt source and the target overall load for the processor. For example, each processor can maintain information about each interrupt it processes over time. The operating system receives this historical load information to determine an expected load for interrupts of a given type from a given device, an overall load on the system, and a target load for each processor. Given a set of interrupt sources, their expected loads, and target load for each processor, each interrupt source can be assigned dynamically to a processor during runtime of the system. These assignments can be changed given current operating conditions of the system.
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Youssef M Barakat from Redmond, WA, age ~46 Get Report