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Yong Ming Qin

from Union City, CA
Age ~69
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Also known as:
Yong M Qin, Yong Wei Huang Qin, Young M Qin, Yongming M Qin, Yongm M Qin, Yong M Oin, Qin Young
Phone and address:
4601 Queen Anne Ct, Union City, CA 94587
Related to:
Cecelia O Young, 75Vincent Liu, 29Yi YongKodie Lee, 39William YoungYong K Li, 48
Connected to:
Bin Y Qin, 60Chin F Qin, 69Christine H Qin, 56Cong C Qin, 53Da G Qin, 67Dennis B Qin, 38Fen H Qin, 61Guo H Qin, 41Henry Qin, 35Huiqing Qin, 53

Yong Qin Phones & Addresses

  • 4601 Queen Anne Ct, Union City, CA 94587
  • La Plata, MD
  • White Plains, MD
  • 4800 Kingfisher Ct, Waldorf, MD 20603
  • Vienna, VA
  • Montgomery Village, MD
  • 3541 Silent Creek Rd, White Plains, MD 20695

Public records

Vehicle Records

Yong Qin

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Address:
3541 Silent Crk Rd, White Plains, MD 20695
VIN:
4T1BK46K47U537911
Make:
TOYOTA
Model:
CAMRY
Year:
2007

Resumes

Resumes

Yong Qin Photo 1

Yong Qin

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Position:
HPC User Services Consultant at Lawrence Berkeley National Laboratory, UC Berkeley
Location:
San Francisco Bay Area
Industry:
Research
Work:
Lawrence Berkeley National Laboratory, UC Berkeley since 2009
HPC User Services Consultant
QLogic 2008 - 2009
Performance Engineer
QLogic (formerly Silverstorm Technologies) 2006 - 2008
Applications Engineer
SilverStorm Technologies 2006 - 2006
Applications Engineer
The Pennsylvania State University 2006 - 2006
Postdoctoral Scholar
Education:
Penn State University 2000 - 2005
Tsinghua University 1997 - 2000
Tsinghua University 1992 - 1997
Yong Qin Photo 2

Computer Hardware Professional

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Location:
San Francisco Bay Area
Industry:
Computer Hardware
Yong Qin Photo 3

Yong Qin

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Location:
San Francisco Bay Area
Industry:
Computer Hardware
Yong Qin Photo 4

Yong Qin

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Location:
United States
Yong Qin Photo 5

Ic Design Engineer At Oracle

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Position:
Principal IC Design Engineer at Oracle Corporation
Location:
San Jose, California
Industry:
Computer Hardware
Work:
Oracle Corporation since Feb 2010
Principal IC Design Engineer
Sun Microsystems Jun 2001 - Feb 2010
Staff IC Design Engineer
Education:
Michigan State University 1999 - 2000
Tsinghua University 1994 - 1999
B.S., E.E.

Publications

Us Patents

Method And Mechanism To Determine Keeper Size

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US Patent:
7298177, Nov 20, 2007
Filed:
Apr 29, 2005
Appl. No.:
11/118897
Inventors:
Yonghee Im - Pleasanton CA, US
Yong Qin - Sunnyvale CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
H03K 19/096
US Classification:
326121, 326 98
Abstract:
A method and apparatus for determining the size of a keeper transistor in a dynamic circuit is provided. A first portion of a dynamic circuit, comprising the keeper transistor, is analyzed to determine keeper current data that describes what size the keeper transistor would need to be to supply a specified amount of keeper current. A second portion of the dynamic circuit is analyzed, separate from the first portion, to determine an estimated amount of leakage current that passes through the PDN when the PDN is not actively discharging the dynamic node may be determined. The size for the keeper transistor that enables the keeper transistor, when activated, to produce an amount of keeper current that is substantially equal to the estimated amount of leakage current may be determined based on the analysis performed on the first and second portion.

Collective Communication System And Methods

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US Patent:
20200274733, Aug 27, 2020
Filed:
Feb 13, 2020
Appl. No.:
16/789458
Inventors:
- Raanana, IL
Lion Levi - Yavne, IL
Gil Bloch - Zichron Yaakov, IL
Daniel Marcovitch - Haifa, IL
Noam Bloch - Bat Shlomo, IL
Yong Qin - Lafayette CA, US
Yaniv Blumenfeld - Haifa, IL
Eitan Zahavi - Zichron Yaakov, IL
International Classification:
H04L 12/40
G06F 12/02
H04W 88/06
H04W 24/10
H04B 7/0456
H04L 12/44
Abstract:
A method in which a plurality of process are configured to hold a block of data destined for other processes, with data repacking circuitry including receiving circuitry configured to receive at least one block of data from a source process of the plurality of processes, the repacking circuitry configured to repack received data in accordance with at least one destination process of the plurality of processes, and sending circuitry configured to send the repacked data to the at least one destination process of the plurality of processes, receiving a set of data for all-to-all data exchange, the set of data being configured as a matrix, the matrix being distributed among the plurality of processes, and transposing the data by each of the plurality of processes sending matrix data from the process to the repacking circuitry, and the repacking circuitry receiving, repacking, and sending the resulting matrix data to destination processes.
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Yong Ming Qin from Union City, CA, age ~69 Get Report