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Ying Feng Tai

from Las Vegas, NV
Age ~77

Ying Tai Phones & Addresses

  • 8104 Chevoit Ct, Las Vegas, NV 89129 (702) 396-6928
  • 9305 Thunder Falls Ct, Las Vegas, NV 89149
  • Santa Clara, CA
  • Cupertino, CA
  • Baltimore, MD
  • East Windsor, NJ
  • 8104 Chevoit Ct, Las Vegas, NV 89129

Publications

Us Patents

Adaptive Read Comparison Signal Generation For Memory Systems

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US Patent:
20130117616, May 9, 2013
Filed:
Aug 31, 2012
Appl. No.:
13/602039
Inventors:
YING YU TAI - Mountain View CA, US
YUEH YALE MA - Palo Alto CA, US
International Classification:
G11C 29/00
US Classification:
714718, 714E11001
Abstract:
Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values. And some implementations are enabled to determine and utilize shifted read comparison signal values associated with one or more storage medium characterization parameter values and an identified error condition.

Soft Information Generation For Memory Systems

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US Patent:
20130117640, May 9, 2013
Filed:
Aug 31, 2012
Appl. No.:
13/602047
Inventors:
YING YU TAI - Mountain View CA, US
YUEH YALE MA - Palo Alto CA, US
International Classification:
H03M 13/05
US Classification:
714780, 714E11032
Abstract:
Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values. And some implementations are enabled to determine and utilize shifted read comparison signal values associated with one or more storage medium characterization parameter values and an identified error condition.

Statistical Read Comparison Signal Generation For Memory Systems

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US Patent:
20130117613, May 9, 2013
Filed:
Aug 31, 2012
Appl. No.:
13/602031
Inventors:
Ying Yu Tai - Mountain View CA, US
Yueh Yale Ma - Palo Alto CA, US
International Classification:
G06F 12/00
G06F 11/07
US Classification:
714 54, 711154, 711E12001, 714E11024
Abstract:
Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values. And some implementations are enabled to determine and utilize shifted read comparison signal values associated with one or more storage medium characterization parameter values and an identified error condition.

Maintenance Operations For Memory Devices

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US Patent:
20220404969, Dec 22, 2022
Filed:
Jul 7, 2022
Appl. No.:
17/859816
Inventors:
- Boise ID, US
Jiangli Zhu - San Jose CA, US
Fangfang Zhu - San Jose CA, US
Ying Yu Tai - Mountain View CA, US
International Classification:
G06F 3/06
Abstract:
Methods, systems, and devices for performing an access operation on a memory cell, incrementing a value of a first counter based on performing the access operation on the memory cell, determining that the incremented value of the first counter satisfies a threshold, incrementing a value of a second counter based on determining that the incremented value of the first counter satisfies the threshold, and performing a maintenance operation on the memory cell based on determining that the incremented value of the first counter satisfies the threshold are described.

Scanning Techniques For A Media-Management Operation Of A Memory Sub-System

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US Patent:
20220326856, Oct 13, 2022
Filed:
Apr 27, 2022
Appl. No.:
17/730958
Inventors:
- Boise ID, US
Wei Wang - Dublin CA, US
Jiangli Zhu - San Jose CA, US
Ying Yu Tai - Mountain View CA, US
International Classification:
G06F 3/06
Abstract:
Methods, systems, and devices for memory can include techniques for identifying first quantities of write counts for a first plurality of super management units (SMUs) in a mapped region of a memory sub-system, identifying, by a hardware component of the memory sub-system, a first SMU of the first plurality that includes a fewest quantity of write counts of the first quantity of write counts, and performing a wear-leveling operation based at least in part on a first quantity of write counts of the first SMU of the first plurality in the mapped region being less than a second quantity of writes counts of a second SMU of a second plurality of SMUs in an unmapped region of the memory sub-system.

Performing Hybrid Wear Leveling Operations Based On A Sub-Total Write Counter

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US Patent:
20220308767, Sep 29, 2022
Filed:
Jun 13, 2022
Appl. No.:
17/839293
Inventors:
- Boise ID, US
Jiangli Zhu - San Jose CA, US
Ning Chen - San Jose CA, US
Ying Yu Tai - Mountain View CA, US
International Classification:
G06F 3/06
G06F 12/10
Abstract:
An example method may include performing a first wear leveling operation on a group of data blocks based on a write counter associated with the group of data blocks, wherein the first wear leveling operation comprises including the group of data blocks in a plurality of groups of mapped data blocks, responsive to including the group of data blocks in the plurality of groups of mapped data blocks, performing a second wear leveling operation on the group of data blocks, wherein performing the second wear leveling operation comprises determining a base address of the group of data blocks, the base address indicating a location at which the group of data blocks begins, and accessing a data block in the group of data blocks based on the base address of the group of data blocks and a logical address associated with the data block.

Hardware Based Status Collector Acceleration Engine For Memory Sub-System Operations

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US Patent:
20220283744, Sep 8, 2022
Filed:
Mar 24, 2022
Appl. No.:
17/703902
Inventors:
- Boise ID, US
Jiangli Zhu - San Jose CA, US
Ying Tai - Mountain View CA, US
Wei Wang - Dublin CA, US
International Classification:
G06F 3/06
G06F 11/10
Abstract:
Methods, systems, and devices for one or more acceleration engines for memory sub-system operations are described. An acceleration engine can perform one or more validation procedures on one or more codewords of a management unit. The acceleration engine can collect validation data for the management unit based on performing the validation procedures. The acceleration engine can aggregate the validation data into group validation data associated with a set of management units. The acceleration engine can transmit the group validation data to firmware of a memory sub-system or a host device.

Maintaining Data Consistency In A Memory Sub-System That Uses Hybrid Wear Leveling Operations

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US Patent:
20220206941, Jun 30, 2022
Filed:
Mar 18, 2022
Appl. No.:
17/698424
Inventors:
- Boise ID, US
Jiangli Zhu - San Jose CA, US
Ying Yu Tai - Mountain View CA, US
International Classification:
G06F 12/02
G06F 3/06
Abstract:
A processing device in a memory sub-system maintains a mapping data structure to track data movements from a plurality of data management units associated with a media management operation on a memory device. The processing device further uses a first indicator and a second indicator of a plurality of indicators to indicate which data of data management units of a source group of data management units have been copied to a destination group of data management units during the media management operation. Data located in data management units preceding the first indicator have been copied to data management units of the destination group of data management units. Data located in data management units associated with the first indicator and the second indicator or between the first indicator and the second indicator are either copied to data management units of the destination group of data management units or remain located in data management units of the source group of data management units. Data located in data management units subsequent to the second indicator remain located in data management units of the source group of data management units and have not been copied to the destination group of data management units.
Ying Feng Tai from Las Vegas, NV, age ~77 Get Report