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Yi Ma

from San Mateo, CA
Age ~48
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Also known as:
Yi Zhao, Mi Yi
Phone and address:
818 Magellan Ln, San Mateo, CA 94404
Related to:
Regina C Galang, 53Maricarmen Moreno, 69Manuel Quiogue, 53Eleanor C Galang, 77
Connected to:
Ah N Ma, 70Aileen B Ma, 51Akana K Ma, 68Alex B Ma, 49Alexandra Ma, 33Allan Ma, 38Anni Ma, 39Annie Ma, 49Athena Ma, 30Ayan S Ma, 38

Yi Ma Phones & Addresses

  • 818 Magellan Ln, San Mateo, CA 94404
  • Foster City, CA
  • Cupertino, CA
  • Belmont, CA
  • 1023 Hampton St, Atlanta, GA 30318 (404) 870-0833
  • 1004 Curran St, Atlanta, GA 30318 (404) 870-0833

Resumes

Resumes

Yi Ma Photo 1

Software Td At Dr. D Studios

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Location:
San Francisco Bay Area
Industry:
Animation
Yi Ma Photo 2

Software Engineer

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Location:
327400 Georgia Tech Sta, Atlanta, GA
Industry:
Internet
Work:
Google
Software Engineer
Acxiom
Architect
Deem, Inc.
Principal Software Engineer
Deem, Inc. Sep 2011 - Apr 2013
Senior Software Engineer
Oracle Jan 2007 - Sep 2011
Senior Software Engineer
Education:
Carnegie Mellon University's College of Engineering 2013 - 2015
Masters, Computer Engineering Huazhong University of Science and Technology 2009 - 2013
Bachelor of Engineering, Bachelors Georgia Institute of Technology 2001 - 2004
Master of Science, Masters, Computer Science Shanghai Jiao Tong University 1994 - 2001
Master of Science, Masters, Bachelors, Bachelor of Science, Computer Science
Skills:
Java
Python
C
Cuda
Hadoop
Latex
C++
Javascript
Ruby
Html/Css
Machine Learning
Deep Learning
Computer Vision
Algorithms
Distributed Systems
Software Engineering
Spring
Java Enterprise Edition
Agile Methodologies
Web Services
Jdbc
Xml
Hibernate
Tomcat
Oracle
Linux
Pl/Sql
Perl
Json
Restful Webservices
Design Patterns
Oo Software Development
Soa
Oracle Sql Developer
Eclipse
Subversion
Maven
Html
Apache
Mongodb
Multithreading
Jdeveloper
Perforce
Jira
Jenkins
Cvs
Solaris
Mac
Windows
Jboss Resteasy
Database Design
Performance Tuning
Interests:
Drawing
Languages:
Mandarin
English
Yi Ma Photo 3

Yi Ma

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Yi Ma Photo 4

Yi Ma

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Location:
San Mateo, California
Industry:
Internet
Skills:
Software Engineering
Java Enterprise Edition
Distributed Systems
Java
Agile Methodologies
C++
PL/SQL
JDBC
Perl
JavaScript
HTML
XML
JSON
RESTful WebServices
Spring
Hibernate
Apache
Tomcat
Design Patterns
OO Software Development
SOA
Web Services
Oracle
MongoDB
Oracle SQL Developer
Multithreading
Eclipse
JDeveloper
Perforce
JIRA
Jenkins
Subversion
CVS
Linux
Solaris
Mac
Windows
Maven
jboss Resteasy
Database Design
Performance Tuning

Publications

Us Patents

Gate Electrode Dopant Activation Method For Semiconductor Manufacturing Including A Laser Anneal

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US Patent:
7078302, Jul 18, 2006
Filed:
Feb 23, 2004
Appl. No.:
10/784904
Inventors:
Yi Ma - Santa Clara CA, US
Khaled Z. Ahmed - Anaheim CA, US
Kevin L. Cunningham - Mountain View CA, US
Robert C. McIntosh - San Jose CA, US
Abhilash J. Mayur - Salinas CA, US
Haifan Liang - Oakland CA, US
Mark Yam - Monte Sereno CA, US
Toi Yue Becky Leung - Sunnyvale CA, US
Christopher Olsen - Fremont CA, US
Shulin Wang - Campbell CA, US
Majeed Foad - Sunnyvale CA, US
Gary Eugene Miner - Fremont CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/336
H01L 21/22
H01L 21/38
H01L 21/3205
H01L 21/4763
US Classification:
438299, 438308, 438530, 438585
Abstract:
In one embodiment, the invention generally provides a method for annealing a doped layer on a substrate including depositing a polycrystalline layer to a gate oxide layer and implanting the polycrystalline layer with a dopant to form a doped polycrystalline layer. The method further includes exposing the doped polycrystalline layer to a rapid thermal anneal to readily distribute the dopant throughout the polycrystalline layer. Subsequently, the method includes exposing the doped polycrystalline layer to a laser anneal to activate the dopant in an upper portion of the polycrystalline layer.

Hetero-Structure Variable Silicon Rich Nitride For Multiple Level Memory Flash Memory Device

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US Patent:
7602067, Oct 13, 2009
Filed:
Dec 17, 2007
Appl. No.:
11/957787
Inventors:
Yi Ma - Santa Clara CA, US
Robert Ogle - San Jose CA, US
Assignee:
Spansion LLC - Sunnyvale CA
International Classification:
H01L 29/40
US Classification:
257760, 257E29309, 257325
Abstract:
Charge storage stacks containing hetero-structure variable silicon richness nitride for memory cells and methods for making the charge storage stacks are provided. The charge storage stack can contain a first insulating layer on a semiconductor substrate; n charge storage layers comprising silicon-rich silicon nitride on the first insulating layer, wherein numbers of the charge storage layers increase from the bottom to the top and a k-value of an n−1th charge storage layer is higher than a k-value of an nth charge storage layer; n−1 dielectric layers comprising substantially stoichiometric silicon nitride between each of the n charge storage layers; and a second insulating layer on the nth charge storage layers.

Gate Electrode Dopant Activation Method For Semiconductor Manufacturing

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US Patent:
7611976, Nov 3, 2009
Filed:
Jul 5, 2006
Appl. No.:
11/428758
Inventors:
Yi Ma - Santa Clara CA, US
Khaled Z. Ahmed - Anaheim CA, US
Kevin L. Cunningham - Mountain View CA, US
Robert C. McIntosh - San Jose CA, US
Abhilash J. Mayur - Salinas CA, US
Haifan Liang - Oakland CA, US
Mark Yam - Monte Sereno CA, US
Toi Yue Becky Leung - Sunnyvale CA, US
Christopher Olsen - Fremont CA, US
Shulin Wang - Campbell CA, US
Majeed Foad - Sunnyvale CA, US
Gary Eugene Miner - Fremont CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/425
US Classification:
438530, 438532, 257E21347
Abstract:
Embodiments of the invention generally provide a method for forming a doped silicon-containing material on a substrate. In one embodiment, the method provides depositing a polycrystalline layer on a dielectric layer and implanting the polycrystalline layer with a dopant to form a doped polycrystalline layer having a dopant concentration within a range from about 1×10atoms/cmto about 1×10atoms/cm, wherein the doped polycrystalline layer contains silicon or may contain germanium, carbon, or boron. The substrate may be heated to a temperature of about 800 C. or higher, such as about 1,000 C. , during the rapid thermal anneal. Subsequently, the doped polycrystalline layer may be exposed to a laser anneal and heated to a temperature of about 1,000 C. or greater, such within a range from about 1,050 C. to about 1,400 C.

Atomic Layer Deposition Processes For Non-Volatile Memory Devices

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US Patent:
7659158, Feb 9, 2010
Filed:
Mar 31, 2008
Appl. No.:
12/059782
Inventors:
Yi Ma - Santa Clara CA, US
Shreyas S. Kher - Campbell CA, US
Khaled Ahmed - Anaheim CA, US
Tejal Goyani - Sunnyvale CA, US
Maitreyee Mahajani - Saratoga CA, US
Jallepally Ravi - Santa Clara CA, US
Yi-Chiau Huang - Fremont CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/8238
H01L 29/788
US Classification:
438201, 438211, 257315, 257E21179, 257E29123
Abstract:
Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer.

Integrated Circuit Fabrication Process With Minimal Post-Laser Annealing Dopant Deactivation

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US Patent:
7737036, Jun 15, 2010
Filed:
Aug 9, 2007
Appl. No.:
11/836267
Inventors:
Yi Ma - Santa Clara CA, US
Philip Allan Kraus - San Jose CA, US
Christopher Sean Olsen - Fremont CA, US
Khaled Z. Ahmed - Anaheim CA, US
Abhilash J. Mayur - Salinas CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/44
US Classification:
438683, 438533, 438662, 438664, 257E21002
Abstract:
Post-laser annealing dopant deactivation is minimized by performing certain low temperature process steps prior to laser annealing.

Integrated Circuit Fabrication Process Using A Compression Cap Layer In Forming A Silicide With Minimal Post-Laser Annealing Dopant Deactivation

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US Patent:
7863193, Jan 4, 2011
Filed:
Aug 9, 2007
Appl. No.:
11/836326
Inventors:
Yi Ma - Santa Clara CA, US
Philip Allan Kraus - San Jose CA, US
Christopher Sean Olsen - Fremont CA, US
Khaled Z. Ahmed - Anaheim CA, US
Abhilash J. Mayur - Salinas CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/44
US Classification:
438683, 438533, 438637, 438672, 438E21002
Abstract:
Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying compression cap layer, to prevent metal agglomeration at the silicon melting temperature. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing near the silicon melting temperature.

Methods For Manufacturing High Dielectric Constant Film

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US Patent:
7871942, Jan 18, 2011
Filed:
Mar 27, 2008
Appl. No.:
12/057113
Inventors:
Shreyas S. Kher - Campbell CA, US
Pravin K. Narwankar - Sunnyvale CA, US
Khaled Z. Ahmed - Anaheim CA, US
Yi Ma - Santa Clara CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/31
H01L 21/469
US Classification:
438785, 438786, 257E21625, 42725519, 42725531
Abstract:
Processes for making a high K (dielectric constant) film using an ultra-high purity hafnium containing organometallic compound are disclosed. Also described are devices incorporating high K films made with high purity hafnium containing organometallic compounds.

Integrated Scheme For Forming Inter-Poly Dielectrics For Non-Volatile Memory Devices

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US Patent:
7910446, Mar 22, 2011
Filed:
Jun 27, 2008
Appl. No.:
12/163542
Inventors:
Yi Ma - Santa Clara CA, US
Shreyas Kher - Campbell CA, US
Khaled Ahmed - Anaheim CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/336
US Classification:
438287, 438216, 438261, 438591
Abstract:
Electronic devices and methods for forming electronic devices that allow for a reduction in device dimensions while also maintaining or reducing leakage current for non-volatile memory devices are provided. In one embodiment, a method of fabricating a non-volatile memory device is provided. The method comprises depositing a floating gate polysilicon layer on a substrate, forming a silicon oxide layer on the floating gate polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a high-k dielectric material layer on the first silicon oxynitride layer, depositing a second silicon oxynitride on the high-k dielectric material, and forming a control gate polysilicon layer on the second silicon oxynitride layer. In one embodiment, the high-k dielectric material layer comprises hafnium silicon oxynitride.

Isbn (Books And Publications)

An Invitation to 3-D Vision: From Images to Geometric Models

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Author

Yi Ma

ISBN #

0387008934

Dynamical Vision: ICCV 2005 and ECCV 2006 Workshops, WDV 2005 and WDV 2006, Beijing, China, October 21, 2005, Graz, Austria, May 13, 2006, Revised Papers

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Author

Yi Ma

ISBN #

3540709312

Control profile
Yi Ma from San Mateo, CA, age ~48 Get Report