Search

Yaron Shragai

from Waltham, MA
Age ~53
Get Report
Also known as:
Yaron Shragal, Shragai Yaron, Yaron I
Phone and address:
37 Lakeview Ter, Waltham, MA 02451
(781) 647-5487
Connected to:
Uri Shragai, 81Daniel B Shrage, 52Paul H Shrage, 93Conrad Shrager, 36Scott A Shragg, 61Abraham J Shragge, 74Jordan T Shrago, 34Joseph B Shrago, 93Charles Z Shraibman, 47Joseph K Shraibman, 46

Yaron Shragai Phones & Addresses

  • 37 Lakeview Ter, Waltham, MA 02451 (781) 647-5487
  • 27 Lakeview Ter, Waltham, MA 02451
  • 17 Avon St, Natick, MA 01760 (508) 653-1347
  • 1021 Rolland Moore Dr, Fort Collins, CO 80526
  • 4470 Lemay Ave, Fort Collins, CO 80525 (970) 282-9326
  • Rancho Cordova, CA
  • 6751 198Th St, Fresh Meadows, NY 11365 (718) 454-0725 (718) 454-9593
  • Flushing, NY

Work

Company: Draper laboratory Nov 2016 Position: Principal system software security r and d engineer

Education

Degree: Masters, Master of Engineering School / High School: The Cooper Union For the Advancement of Science and Art 1994 to 1996 Specialities: Engineering

Skills

Firmware • Low Level Programming • Computer Architecture • Microarchitecture • Assembly Language • Embedded Systems • C • Perl • System on A Chip • Supervisory Skills • Server Architecture • Microcontrollers • Debugging • Product Development • Technical Documentation • Semiconductors • Electronics • Hardware Architecture • Microprocessors • System Architecture • Processors • Embedded Software • Programming • X86 Assembly • X86 • Intel • C++ • Team Leadership • Engineering Management • Engineering • Verilog • Integration

Languages

English • Hebrew • French • German • Greek

Industries

Computer Hardware

Resumes

Resumes

Yaron Shragai Photo 1

Principal System Software Security R And D Engineer

View page
Location:
Waltham, MA
Industry:
Computer Hardware
Work:
Draper Laboratory
Principal System Software Security R and D Engineer
Intel Corporation Apr 2008 - May 2016
Senior Staff Firmware Engineer: Processor Uncore Microcontroller Firmware
Intel Corporation Jan 2006 - Jun 2008
Senior Firmware Engineer: Processor Core Microcode
Intel Corporation Mar 1999 - Dec 2005
Senior Firmware Engineer: Itanium Processor Family Pal
Intel Corporation Sep 1997 - Feb 1999
Processor Hardware Design Engineer
Education:
The Cooper Union For the Advancement of Science and Art 1994 - 1996
Masters, Master of Engineering, Engineering The Cooper Union For the Advancement of Science and Art 1989 - 1994
Bachelor of Engineering, Bachelors, Electronics Engineering Bronx High School of Science 1986 - 1989
Skills:
Firmware
Low Level Programming
Computer Architecture
Microarchitecture
Assembly Language
Embedded Systems
C
Perl
System on A Chip
Supervisory Skills
Server Architecture
Microcontrollers
Debugging
Product Development
Technical Documentation
Semiconductors
Electronics
Hardware Architecture
Microprocessors
System Architecture
Processors
Embedded Software
Programming
X86 Assembly
X86
Intel
C++
Team Leadership
Engineering Management
Engineering
Verilog
Integration
Languages:
English
Hebrew
French
German
Greek

Publications

Us Patents

Method Of Handling Errors

View page
US Patent:
7370231, May 6, 2008
Filed:
Dec 14, 2004
Appl. No.:
11/012979
Inventors:
Tryggve Fossum - Northborough MA, US
Yaron Shragai - Waltham MA, US
Shubhendu S. Mukherjee - Framingham MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 11/00
US Classification:
714 10
Abstract:
An error handling routine of a processor, executing in response to a first detected unrecoverable error (DUE) of the processor, responding to an indication that a second DUE has occurred by evaluating the effect of the second DUE on the correctness of the error handling routine.

Converting Merge Buffer System-Kill Errors To Process-Kill Errors

View page
US Patent:
7380169, May 27, 2008
Filed:
Sep 24, 2004
Appl. No.:
10/948904
Inventors:
Tryggve Fossum - Northborough MA, US
Yaron Shragai - Natick MA, US
Ugonna Echeruo - Worcester MA, US
Shubhendu S. Mukherjee - Framingham MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 11/00
US Classification:
714 36
Abstract:
An apparatus includes a buffer that collects store instruction information associated with one or more processes. The collected store instruction information includes data and addresses where the data are to be stored. The apparatus also includes a buffer control that drains the buffer of store instructions associated with a first process before it collects store instructions associated with a second process.

Poisoned Error Signaling For Proactive Os Recovery

View page
US Patent:
20050138487, Jun 23, 2005
Filed:
Dec 8, 2003
Appl. No.:
10/728836
Inventors:
Kushagra Vaid - San Jose CA, US
Suresh Marisetty - San Jose CA, US
Yaron Shragai - Natick MA, US
Koichi Yamada - Los Gatos CA, US
Rajendra Kuramkote - Newcastle WA, US
Scott Brenden - Bothell WA, US
Assignee:
Intel Corporation (a Delaware corporation) - Santa Clara CA
International Classification:
G06F011/00
US Classification:
714052000
Abstract:
Use of data poisoning techniques may permit proactive operating system recovery without needing to always bringing down the operating system when uncorrectable errors are encountered.
Control profile
Yaron Shragai from Waltham, MA, age ~53 Get Report