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Yanzhong Xu

from Newark, CA
Age ~62
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Related to:
Xiuyu Gao, 62Yiqin Xu, 37
Connected to:
Ailan Xu, 56Aimin Xu, 47Alison Xu, 30Amelia Xu, 37Amy J Xu, 39Angelina S Xu, 38Anthony X Xu, 58Beilei Xu, 54Benjamin Xu, 42Bingjun Xu, 42

Yanzhong Xu Phones & Addresses

  • Newark, CA
  • 1756 Townsend Ave, Santa Clara, CA 95051 (408) 241-4832

Resumes

Resumes

Yanzhong Xu Photo 1

Information Technology And Services Consultant And Contractor

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Position:
Oracle Application Consultant at Yahoo!, Independent Consultant at Independent Consultant (Self-employed)
Location:
San Francisco Bay Area
Industry:
Information Technology and Services
Work:
Yahoo! since Jan 2006
Oracle Application Consultant
Independent Consultant (Self-employed) since Oct 2004
Independent Consultant
Equinix 2008 - 2008
consultant
Yanzhong Xu Photo 2

Yanzhong Xu

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Location:
San Francisco Bay Area
Industry:
Electrical/Electronic Manufacturing

Publications

Us Patents

Metal-Oxide-Semiconductor Varactors

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US Patent:
7276746, Oct 2, 2007
Filed:
Jun 27, 2005
Appl. No.:
11/169070
Inventors:
Yanzhong Xu - Santa Clara CA, US
Jeffrey T. Watt - Palo Alto CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H01L 29/80
H01L 31/112
US Classification:
257258, 257199
Abstract:
Integrated circuit varactors and methods for varactor fabrication are provided. Varactors are formed on integrated circuits that contain complementary metal-oxide-semiconductor (CMOS) transistors. The same semiconductor fabrication process steps are used to form both the varactors and CMOS transistors, thereby eliminating potentially cost-prohibitive changes to manufacturing process flows. Varactor performance is enhanced by including a deep n-well structure. The deep n-well reduces sheet resistance in the semiconductor portion of the varactor and improves the varactor's quality factor. The deep n-well is formed from the same deep n-well layer that is used to form the CMOS transistors on the integrated circuit. The varactor has two active electrodes. The electrodes are spaced farther apart than specified by semiconductor fabrication design rules.

Latch Circuit

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US Patent:
7388772, Jun 17, 2008
Filed:
Mar 20, 2006
Appl. No.:
11/385531
Inventors:
Yanzhong Xu - Santa Clara CA, US
Jeffrey T. Watt - Palo Alto CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G11C 11/00
US Classification:
365154, 365156, 36518905
Abstract:
A latch circuit comprises eight MOS transistors in which a first pair of transistors are connected in series between a voltage supply node and ground and a second pair of transistors are connected in parallel to the first pair between the voltage supply node and ground. A fifth transistor is connected between the gates of the first pair and a node between the transistors of the second pair and a sixth transistor is connected between the gates of the second pair and a node between the transistors of the first pair. The seventh transistor is a write transistor connected between a data in line and the node between the first pair of transistors and the eighth transistor is a clear transistor connected between the node between the second pair of transistors and ground.

Test Structure And Method For Measuring Mismatch And Well Proximity Effects

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US Patent:
7586322, Sep 8, 2009
Filed:
May 2, 2007
Appl. No.:
11/743567
Inventors:
Yanzhong Xu - Santa Clara CA, US
Jeffrey T. Watt - Palo Alto CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G01R 31/26
G01R 31/02
US Classification:
324769, 438 14, 438 17, 716 4
Abstract:
The present invention is directed to a test structure and method to determine the effects of the well proximity effect on the gate threshold voltage of FETs at different distances from the edge of the well.

Write Margin Calculation Tool For Dual-Port Random-Access-Memory Circuitry

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US Patent:
7689941, Mar 30, 2010
Filed:
May 11, 2007
Appl. No.:
11/803091
Inventors:
Teng Chow Ooi - Penang, MY
Yanzhong Xu - Santa Clara CA, US
Jeffrey T. Watt - Palo Alto CA, US
Haiming Yu - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 2, 716 1, 716 3, 716 18, 703 14
Abstract:
Systems and methods are provided for computing write margins for dual-port memory. A design for a dual-port memory array cell is generated using a circuit design tool. A user modifies the design of the dual-port memory array cell to incorporate two voltage sources. The voltage sources are used to represent differential noise on the memory cell. A write margin calculation tool uses a circuit simulation tool to perform transient simulations of write-during-read operations on the modified dual-port memory array cell. During the transient simulations, the voltage level on the voltages sources is systematically varied. The write margin for the dual-port memory is determined by analyzing the results of the transient simulations for each of the voltage levels used for the voltage sources.

Angled Implantation For Deep Submicron Device Optimization

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US Patent:
7883946, Feb 8, 2011
Filed:
May 8, 2008
Appl. No.:
12/151646
Inventors:
Che Ta Hsu - San Jose CA, US
Christopher J. Pass - San Jose CA, US
Dale Ibbotson - Pleasanton CA, US
Jeffrey T. Watt - Palo Alto CA, US
Yanzhong Xu - Santa Clara CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H01L 21/84
H01L 21/22
H01L 21/38
US Classification:
438163, 438302, 438369, 438514, 438525, 438531, 257547, 257E21618, 257E21633
Abstract:
A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.

Volatile Memory Elements With Soft Error Upset Immunity

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US Patent:
8077500, Dec 13, 2011
Filed:
Jun 22, 2010
Appl. No.:
12/820410
Inventors:
Yanzhong Xu - Santa Clara CA, US
Jeffrey T. Watt - Palo Alto CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G11C 11/00
G11C 5/14
US Classification:
365154, 365156, 365226, 365227, 365228, 365229
Abstract:
Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.

Volatile Memory Elements With Soft Error Upset Immunity

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US Patent:
8355292, Jan 15, 2013
Filed:
Sep 30, 2009
Appl. No.:
12/571143
Inventors:
Yanzhong Xu - Santa Clara CA, US
Jeffrey T. Watt - Palo Alto CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G11C 5/14
US Classification:
365226, 365154, 36518507, 36518508, 36518909
Abstract:
Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.

Integrated Circuits With Asymmetric And Stacked Transistors

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US Patent:
8482963, Jul 9, 2013
Filed:
Dec 2, 2009
Appl. No.:
12/629831
Inventors:
Jun Liu - Santa Clara CA, US
Yanzhong Xu - Santa Clara CA, US
Shankar Sinha - Redwood City CA, US
Shih-Lin S. Lee - San Jose CA, US
Jeffrey Xiaoqi Tung - Milpitas CA, US
Albert Ratnakumar - San Jose CA, US
Qi Xiang - San Jose CA, US
Irfan Rahim - Milpitas CA, US
Andy L. Lee - San Jose CA, US
Jeffrey T. Watt - Palo Alto CA, US
Srinivas Perisetty - Santa Clara CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G11C 11/00
US Classification:
365154, 365156
Abstract:
Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.
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Yanzhong Xu from Newark, CA, age ~62 Get Report