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Yang Ni

from Fremont, CA
Age ~44
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Also known as:
Ni I Yang, Amanda Yang, Joanne N Yang, Yan G Ni, Young Ni
Related to:
Sung Mi Youn, 64
Connected to:
Alice Ni, 30Angela C Ni, 45Ba Ni, 72Boo R Ni, 50Carolyn L Ni, 65Chi Ni, 104Chris Ni, 36Ella O Ni, 49Fanqi Ni, 35Hu Ni, 44

Yang Ni Phones & Addresses

  • Fremont, CA
  • Irvine, CA
  • Rowland Heights, CA
  • Diamond Bar, CA
  • Lowell, MA
  • Flushing, NY
  • Monterey Park, CA
  • Rowland Heights, CA
  • Chino Hills, CA

Work

Company: Aurora abidance design Jan 2014 Position: Junior interior designer

Education

School / High School: WEST COLLEGE SCOTLAND- Ipoh 2011 Specialities: Advanced Diploma in collaboration

Resumes

Resumes

Yang Ni Photo 1

Yang Ni

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Yang Ni Photo 2

Yang Ni

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Work:
AURORA ABIDANCE DESIGN

Jan 2014 to Apr 2014
Junior Interior Designer
DRAFTPERSON

Dec 2012 to Jun 2013
FREELANCER
ALAIN DELON

Jun 2012 to Dec 2012
PART TIME PROMOTER
PONEY

Dec 2010 to Mar 2011
PROMOTER
Education:
WEST COLLEGE SCOTLAND
Ipoh
2011 to 2014
Advanced Diploma in collaboration

Business Records

Name / Title
Company / Classification
Phones & Addresses
Yang Ni
Manager
Network Health
Medical Doctor's Office
101 Sta Lndg, Medford, MA 02155
(888) 257-1985

Publications

Us Patents

Mechanisms To Accelerate Transactions Using Buffered Stores

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US Patent:
8316194, Nov 20, 2012
Filed:
Dec 15, 2009
Appl. No.:
12/638054
Inventors:
Ali-Reza Adl-Tabatabai - San Jose CA, US
Yang Ni - Sunnyvale CA, US
Bratin Saha - Santa Clara CA, US
Vadim Bassin - Raanana, IL
Gad Sheaffer - Haifa, IL
David Callahan - Seattle WA, US
Jan Gray - Bellevue WA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
G06F 12/08
G06F 12/16
US Classification:
711154, 711141, 711162, 711E12001, 711E12026, 718101
Abstract:
In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

Unified Optimistic And Pessimistic Concurrency Control For A Software Transactional Memory (Stm) System

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US Patent:
8555016, Oct 8, 2013
Filed:
Dec 17, 2008
Appl. No.:
12/337507
Inventors:
Ali-Reza Adl-Tabatabai - San Jose CA, US
Moshe Bach - Haifa, IL
Sion Berkowits - Nesher, IL
James Henry Cownie - Bristol, GB
Yang Ni - Sunnyvale CA, US
Jeffrey V. Olivier - Champaign IL, US
Bratin Saha - Santa Clara CA, US
Ady Tal - Zichron Yaacov, IL
Adam Wele - Mountain View CA, US
Assignee:
Intel Corporation - santa Clara CA
International Classification:
G06F 12/00
US Classification:
711163, 711168, 711216
Abstract:
A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.

Method And Apparatus To Facilitate Shared Pointers In A Heterogeneous Platform

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US Patent:
8566537, Oct 22, 2013
Filed:
Mar 29, 2011
Appl. No.:
13/074779
Inventors:
Yang Ni - Sunnyvale CA, US
Rajkishore Barik - Houston TX, US
Ali-Reza Adl-Tabatabai - San Jose CA, US
Tatiana Shpeisman - Menlo Park CA, US
Jayanth N. Rao - Folsom CA, US
Ben J. Ashbaugh - Folsom CA, US
Tomasz Janczak - Gdansk, PL
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
G06F 13/00
G06F 13/28
US Classification:
711147, 711137, 711148, 711149, 711150, 711151, 711152, 711153, 711168
Abstract:
A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.

Accelerating A Quiescence Process Of Transactional Memory

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US Patent:
20100057740, Mar 4, 2010
Filed:
Aug 26, 2008
Appl. No.:
12/198852
Inventors:
Yang Ni - Sunnyvale CA, US
Richard Myungon Yoo - Atlanta GA, US
Adam Wojciech Welc - San Francisco CA, US
Bratin Saha - Santa Clara CA, US
Ali-Reza Adl-Tabatabai - Santa Clara CA, US
International Classification:
G06F 9/46
G06F 17/30
G06F 7/00
US Classification:
707 8, 718101, 707E17007
Abstract:
A method to perform validation of a read set of a transaction is presented. In one embodiment, the method compares a read signature of a transaction to a plurality of write signatures associated with a plurality of transactions. The method determines based on the result of comparison, whether to update a local value of the transaction to a commit value of another transaction from the plurality of the transactions.

Accelerating A Quiescence Process Of Transactional Memory

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US Patent:
20100058344, Mar 4, 2010
Filed:
Aug 26, 2008
Appl. No.:
12/198820
Inventors:
Yang Ni - Sunnyvale CA, US
Richard Myungon Yoo - Atlanta GA, US
Adam Wojciech Welc - San Francisco CA, US
Bratin Saha - Santa Clara CA, US
Ali-Reza Adl-Tabatabai - Santa Clara CA, US
International Classification:
G06F 9/46
G06F 17/30
G06F 7/00
US Classification:
718101, 707 8, 707E17007
Abstract:
A method to perform validation of a read set of a transaction is presented. In one embodiment, the method compares a read signature of a transaction to a plurality of write signatures associated with a plurality of transactions. The method determines based on the result of comparison, whether to update a local value of the transaction to a commit value of another transaction from the plurality of the transactions.

Non-Blocking Wait-Free Data-Parallel Scheduler

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US Patent:
20120159495, Jun 21, 2012
Filed:
Dec 17, 2010
Appl. No.:
12/971891
Inventors:
Mohan Rajagopalan - Mountain View CA, US
Ali-Reza Adl-Tabatabai - San Jose CA, US
Yang Ni - Sunnyvale CA, US
Adam Welc - San Francisco CA, US
Richard L. Hudson - Florence MA, US
International Classification:
G06F 9/46
US Classification:
718102
Abstract:
Methods, systems, and mediums are described for scheduling data parallel tasks onto multiple thread execution units of processing system. Embodiments of a lock-free queue structure and methods of operation are described to implement a method for scheduling fine-grained data-parallel tasks for execution in a computing system. The work of one of a plurality of worker threads is wait-free with respect to the other worker threads. Each node of the queue holds a reference to a task that may be concurrently performed by multiple thread execution units, but each on a different subset of data. Various embodiments relate to software-based scheduling of data-parallel tasks on a multi-threaded computing platform that does not perform such scheduling in hardware. Other embodiments are also described and claimed.

Methods And Systems For Mapping A Function Pointer To The Device Code

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US Patent:
20120272210, Oct 25, 2012
Filed:
Apr 22, 2011
Appl. No.:
13/092500
Inventors:
Yang Ni - Sunnyvale CA, US
Ali-Reza Adl-Tabatabai - San Jose CA, US
Tatiana Shpeisman - Menlo Park CA, US
International Classification:
G06F 9/44
G06F 9/45
US Classification:
717106, 717140
Abstract:
Methods for mapping a function pointer to the device code are presented. In one embodiment, a method includes identifying a function which is executable by processing devices. The method includes generating codes including a first code corresponds to a first processing device and a second code corresponds to a second processing device. The second processing device is architecturally different from the first processing device. The method further includes storing the second code in a byte string such that the second code is retrievable if the function will be executed by the second processing device.

Mechanisms To Accelerate Transactions Using Buffered Stores

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US Patent:
20130046924, Feb 21, 2013
Filed:
Oct 23, 2012
Appl. No.:
13/658212
Inventors:
Ali-Reza Adl-Tabatabai - San Jose CA, US
YANG NI - SUNNYVALE CA, US
BRATIN SAHA - SANTA CLARA CA, US
VADIM BASSIN - RAANANA, IL
GAD SHEAFFER - HAIFA, IL
DAVID CALLAHAN - SEATTLE WA, US
JAN GRAY - BELLEVUE WA, US
International Classification:
G06F 12/08
G06F 9/46
US Classification:
711105, 718101, 711141, 711E12026
Abstract:
In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.
Control profile
Yang Ni from Fremont, CA, age ~44 Get Report